SLVSAL1E March   2011  – April 2016 TPS24720

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 THERMAL INFORMATION
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Descriptions
        1. 7.3.1.1  EN
        2. 7.3.1.2  ENSD
        3. 7.3.1.3  FFLTb
        4. 7.3.1.4  FLTb
        5. 7.3.1.5  GATE
        6. 7.3.1.6  GND
        7. 7.3.1.7  IMON
        8. 7.3.1.8  LATCH
        9. 7.3.1.9  OUT
        10. 7.3.1.10 OV
        11. 7.3.1.11 PGb
        12. 7.3.1.12 PROG
        13. 7.3.1.13 SENSE
        14. 7.3.1.14 SET
        15. 7.3.1.15 TIMER
        16. 7.3.1.16 VCC
    4. 7.4 Device Functional Modes
      1. 7.4.1  Board Plug-In
      2. 7.4.2  Inrush Operation
      3. 7.4.3  Action of the Constant-Power Engine
      4. 7.4.4  Circuit Breaker and Fast Trip
      5. 7.4.5  Automatic Restart
      6. 7.4.6  PGb, FLTb, and Timer Operations
      7. 7.4.7  Overtemperature Shutdown
      8. 7.4.8  Start-Up of Hot-Swap Circuit by VCC or EN
      9. 7.4.9  Minimization of Power Dissipation at STANDY by ENSD
      10. 7.4.10 Fault Detection of MOSFET Short With FFLTb
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power-Limited Start-Up
          1. 8.2.2.1.1 STEP 1. Choose RSENSE, RSET, and RIMON
          2. 8.2.2.1.2 STEP 2. Choose MOSFET M1
          3. 8.2.2.1.3 STEP 3. Choose Power-Limit Value, PLIM, and RPROG
          4. 8.2.2.1.4 STEP 4. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT
          5. 8.2.2.1.5 STEP 5. Calculate the Retry-Mode Duty Ratio
          6. 8.2.2.1.6 STEP 6. Select R1, R2, and R3 for UV and OV
          7. 8.2.2.1.7 STEP 7. Choose RGATE, R4, R5, R6, and C1
        2. 8.2.2.2 Additional Design Considerations
          1. 8.2.2.2.1 Use of PGb
          2. 8.2.2.2.2 Output Clamp Diode
          3. 8.2.2.2.3 Gate Clamp Diode
          4. 8.2.2.2.4 High-Gate-Capacitance Applications
          5. 8.2.2.2.5 Bypass Capacitors
          6. 8.2.2.2.6 Output Short-Circuit Measurements
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Revision History

Changes from D Revision (March 2015) to E Revision

  • Changed the Part Number From TPS247120 To: TPS24720 in the Device Information tableGo

Changes from C Revision (September 2013) to D Revision

  • Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go
  • Changed the Input voltage range, PROG - MAX value in the Absolute Maximum Ratings table From: 0.3 To: 3.6 Go
  • Deleted External capacitance - GATE from the Recommended Operating ConditionsGo
  • Deleted text from the last paragraph in the GATE section "If used, any capacitor connecting GATE and GND should not exceed 1 μF and it should be connected in series with a resistor of no less than 1 kΩ."Go
  • Deleted section: Alternative Design Example: GATE Capacitor (dV/dt) Control in Inrush ModeGo
  • Deleted text from the High-Gate-Capacitance Applications section "When gate capacitor dV/dt control is used, ... then a Zener diode is not necessary."Go

Changes from B Revision (May 2011) to C Revision

  • Added Note to Supply Current DisabledGo
  • Added Note to Fast-turnoff delayGo
  • Changed Gate Comparator 6 V to 5.9 V in Functional Block DiagramGo
  • Changed text From :(6 V for VVCC = 12 V) To: (5.9 V for VVCC = 12 V) in the GATE pin descriptionGo
  • Changed Equation 1Go
  • Changed text in the INRUSH OPERATION sectionGo
  • Changed Equation 8Go
  • Added text and new Equation 9Go
  • Changed Equation 11Go
  • Changed text From: VGS rises 6 V To: VGS rises 5.9 VGo
  • Changed text following Equation 11, From: 1.23 ms To 1.22 msGo
  • Changed Equation 15Go
  • Changed text describing Equation 15 and Equation 16 in the Alternative Design Example section. (Equation 15 and Equation 16 deleted by revision F.)Go

Changes from A Revision (April 2011) to B Revision

  • Changed voltages in PGb pin description from 140 mV and 340 mV to 170 mV and 240 mV.Go
  • Changed RIMON equationGo

Changes from * Revision (March 2011) to A Revision