JAJS427I July   2010  – October 2019 TPS63020 , TPS63021

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係
  4. 改訂履歴
  5. 概要 (続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Dynamic Voltage Positioning
      2. 8.3.2 Dynamic Current Limit
      3. 8.3.3 Device Enable
      4. 8.3.4 Power Good
      5. 8.3.5 Overvoltage Protection
      6. 8.3.6 Undervoltage Lockout
      7. 8.3.7 Overtemperature Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Soft-start and Short Circuit Protection
      2. 8.4.2 Buck-Boost Operation
      3. 8.4.3 Control Loop
      4. 8.4.4 Power Save Mode and Synchronization
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design with WEBENCH Tools
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 Input Capacitor Selection
        5. 9.2.2.5 Bypass Capacitor
      3. 9.2.3 Setting The Output Voltage
      4. 9.2.4 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Improved Transient Response for 2 A Load Current
      2. 9.3.2 Supercapacitor Backup Power Supply With Active Cell Balancing
      3. 9.3.3 Low-Power TEC Driver
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 デバイス・サポート
      1. 12.2.1 WEBENCHツールによるカスタム設計
      2. 12.2.2 デベロッパー・ネットワークの製品に関する免責事項
    3. 12.3 ドキュメントのサポート
      1. 12.3.1 関連資料
    4. 12.4 関連リンク
    5. 12.5 サポート・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Control Loop

The controller circuit of the device is based on an average current mode topology. The average inductor current is regulated by a fast current regulator loop which is controlled by a voltage control loop. Figure 5 shows the control loop.

The non-inverting input of the transconductance amplifier, gmv, is assumed to be constant. The output of gmv defines the average inductor current. The inductor current is reconstructed by measuring the current through the high-side buck MOSFET. This current corresponds exactly to the inductor current in boost mode. In buck mode, the current is measured during the on-time of the same MOSFET. During the off-time, the current is reconstructed internally starting from the peak value at the end of the on-time cycle. The average current and the feedback from the error amplifier gmv forms the correction signal gmc. This correction signal is compared to the buck and the boost sawtooth ramp giving the PWM signal. Depending on which of the two ramps, the gmc output crosses either the buck or the boost stage is initiated. When the input voltage is close to the output voltage, one buck cycle is always followed by a boost cycle. In this condition, no more than three cycles in a row of the same mode are allowed. This control method in the buck-boost region ensures a robust control and the highest efficiency.

The buck-boost overlap control makes sure that the classical buck-boost function, which would cause two switches to be on every half a cycle, is avoided. Thanks to this block, whenever all switches becomes active during one clock cycle, the two ramps are shifted away from each other. On the other hand, when there is no switching activities because there is a gap between the ramps, the ramps are moved closer together. As a result, the number of classical buck-boost cycles or no switching is reduced to a minimum and high efficiency values has been achieved.

TPS63020 TPS63021 Averagecurrent_mode_rev3.gifFigure 5. Average Current Mode Control