JAJSNG4B January   2015  – January 2022 TPS65251-1 , TPS65251-2 , TPS65251-3

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics for Buck 1
    7. 6.7 Typical Characteristics for Buck 2
    8. 6.8 Typical Characteristics for Buck 3
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjustable Switching Frequency
      2. 7.3.2  Synchronization
      3. 7.3.3  Out-of-Phase Operation
      4. 7.3.4  Delayed Start-Up
      5. 7.3.5  Soft-Start Time
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Input Capacitor
      8. 7.3.8  Bootstrap Capacitor
      9. 7.3.9  Error Amplifier
      10. 7.3.10 Slope Compensation
      11. 7.3.11 Power Good
      12. 7.3.12 3.3-V and 6.5-V LDO Regulators
      13. 7.3.13 Current Limit Protection
      14. 7.3.14 Overvoltage Transient Protection (OVP)
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low-Power/Pulse Skipping Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Loop Compensation Circuit
        2. 8.2.2.2  Selecting the Switching Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Soft-Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Adjustable Current Limiting Resistor Selection
        9. 8.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 8.2.2.10 Compensation
        11. 8.2.2.11 3.3-V and 6.5-V LDO Regulators
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.1 Loop Compensation Circuit

A typical compensation circuit could be type II (Rc and Cc) to have a phase margin between 60° and 90°, or type III (Rc, Cc and Cff) to improve the converter transient response. CRoll adds a high frequency pole to attenuate high-frequency noise when needed. It may also prevent noise coupling from other rails if there is possibility of cross coupling in between rails when layout is very compact.

GUID-7E193052-74E4-4D34-833A-BB2299CCA58A-low.gifFigure 8-2 Loop Compensation

To calculate the external compensation components use Table 8-1:

Table 8-1 Design Guideline for the Loop Compensation
TYPE II CIRCUITTYPE III CIRCUIT
Select switching frequency that is appropriate for application depending on L, C sizes, output ripple, EMI concerns and etc. Switching frequencies between 500 kHz and 1 MHz give best trade off between performance and cost. When using smaller L and Cs, switching frequency can be increased. To optimize efficiency, switching frequency can be lowered.Type III circuit recommended for switching frequencies higher than 500 kHz.
Select cross over frequency (fc) to be less than 1/5 to 1/10 of switching frequency.Suggested
fc = fs/10		Suggested
fc = fs/10
Set and calculate Rc.
Equation 6. GUID-80D686BA-4B7F-4B60-B3AC-357B413A0EF8-low.gif
Equation 7. GUID-B5D7CEC4-6792-4B67-B9D8-BDB98DC74363-low.gif
Calculate Cc by placing a compensation zero at or before the converter dominant pole
Equation 8. GUID-968DC0AE-B59C-4EDC-8867-AC36DE617DA8-low.gif
Equation 9. GUID-DDB40701-5AD2-4283-99B6-96F480C55180-low.gif
Equation 10. GUID-DDB40701-5AD2-4283-99B6-96F480C55180-low.gif
Add CRoll if needed to remove large signal coupling to high impedance COMP node. Make sure that
Equation 11. GUID-75C30AC8-D12D-469D-AF23-8212A042B970-low.gif
is at least twice the cross over frequency.
Equation 12. GUID-AC3943C4-FA66-4884-91EB-C21E8A51DFF5-low.gif
Equation 13. GUID-AC3943C4-FA66-4884-91EB-C21E8A51DFF5-low.gif
Calculate Cff compensation zero at low frequency to boost the phase margin at the crossover frequency. Make sure that the zero frequency (fzff is smaller than soft-start equivalent frequency (1/Tss).NA
Equation 14. GUID-B6EE359B-A938-49FA-8AF9-01BC4A93103E-low.gif