JAJSQ40A
July 2023 – December 2023
TXV0108-Q1
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics, VCCA = 1.8 ± 0.15 V
5.7
Switching Characteristics, VCCA = 2.5 ± 0.2 V
5.8
Switching Characteristics, VCCA = 3.3 ± 0.3 V
5.9
Typical Characteristics
6
Parameter Measurement Information
6.1
Load Circuit and Voltage Waveforms
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Balanced High-Drive CMOS Push-Pull Outputs
7.3.2
Partial Power Down (Ioff)
7.3.3
VCC Isolation and VCC Disconnect (Ioff-float)
7.3.4
Over-Voltage Tolerant Inputs
7.3.5
Negative Clamping Diodes
7.3.6
Fully Configurable Dual-Rail Design
7.3.7
Supports Timing Sensitive Translation
7.3.8
Wettable Flanks
7.3.9
Integrated Damping Resistor and Impedance Matching
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.3
System Examples
8.3.1
Solving Power Sequencing Challenges with the TXV0108-Q1
8.4
Power Supply Recommendations
8.5
Layout
8.5.1
Layout Guidelines
8.5.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
ドキュメントの更新通知を受け取る方法
9.3
サポート・リソース
9.4
Trademarks
9.5
静電気放電に関する注意事項
9.6
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
RGY|24
サーマルパッド・メカニカル・データ
RGY|24
QFND668
発注情報
jajsq40a_oa
jajsq40a_pm
7
Detailed Description