JAJSQ40A July 2023 – December 2023 TXV0108-Q1
PRODUCTION DATA
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The TXV0108-Q1 not only solves voltage mismatch between interfaces but also solves power sequencing challenges. In some Ethernet applications, you may have a multi-core RGMII system with an Ethernet switch Figure 8-3. In other applications, you may have a standard Ethernet interface with one MAC and PHY. In either case, it is necessary to power up each device properly. This will prevent the I/O pins from powering up before the core blocks, which can cause in-rush current during power up or bus contention and other malfunctions.
With the TXV0108-Q1 supporting the Ioff-float feature, in-rush current from improper power sequencing can be prevented. When either power supply pin is at 0 V or below 100 mV, the I/O pins become high impedance until both pins go above 100 mV. The high impedance state will prevent any in-rush current from flowing to the opposite side.
For additional information on the TXV0108-Q1 and power isolation use cases, see the Solving Power Sequencing Challenges for Ethernet RGMII Communications application note.