JAJSQ40A July   2023  – December 2023 TXV0108-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics, VCCA = 1.8 ± 0.15 V
    7. 5.7 Switching Characteristics, VCCA = 2.5 ± 0.2 V
    8. 5.8 Switching Characteristics, VCCA = 3.3 ± 0.3 V
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Load Circuit and Voltage Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 7.3.2 Partial Power Down (Ioff)
      3. 7.3.3 VCC Isolation and VCC Disconnect (Ioff-float)
      4. 7.3.4 Over-Voltage Tolerant Inputs
      5. 7.3.5 Negative Clamping Diodes
      6. 7.3.6 Fully Configurable Dual-Rail Design
      7. 7.3.7 Supports Timing Sensitive Translation
      8. 7.3.8 Wettable Flanks
      9. 7.3.9 Integrated Damping Resistor and Impedance Matching
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Solving Power Sequencing Challenges with the TXV0108-Q1
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGY|24
サーマルパッド・メカニカル・データ
発注情報

6.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

  • f = 1 MHz
  • ZO = 50 Ω
  • Δt/ΔV ≤ 1 ns/V

GUID-F69EA5FA-85D4-4CF2-BD87-F449FB37C9BE-low.gif
A. CL includes probe and jig capacitance.
Figure 6-1 Load Circuit
Table 6-1 Load Circuit Conditions
ParameterVCCORLCLS1VTP
tpdPropagation (delay) time1.65 V – 3.6 V2 kΩ

15 pF

OpenN/A
ten, tdisEnable time, disable time1.65 V – 3.6 V2 kΩ15 pF2 × VCCO0.15 V
ten, tdisEnable time, disable time1.65 V – 3.6 V2 kΩ15 pFGND0.15 V
GUID-20231113-SS0I-ZPGH-5B6Z-83HNV7CNDJ1J-low.svg
  1. The greater between tPLH and tPHL is the same as tpd.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 6-2 Propagation Delay
GUID-20231113-SS0I-D0WC-MTDR-75FDWK5DDRJS-low.svg
  1. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 6-3 Input and Output Rise and Fall Time
GUID-6D38ACC0-6D77-4DEA-9BC7-BD598F2068FC-low.gif
A. Output waveform on the condition that input is driven to a valid Logic Low.
B. Output waveform on the condition that input is driven to a valid Logic High.
C. VCCO is the supply pin associated with the output port.
D. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 6-4 Enable Time And Disable Time