DLPU125 june 2023
Both the loader and DMD
reset state machines synchronize their operation to an internal sync
pulse in the Apps FPGA. The pulse is one clkd
cycle
in width. The pulse period varies by dmd_type
. For
the DLP9000X devices, there is one sync pulse every five
clkd
cycles. For the DLP6500, there is one
sync pulse every eight clkd
cycles. For each DMD
type, the period indicates the row cycle time – the time required to
load data and issue row-block command for a given DMD row.
The row command and block command state machines in the user DLP control logic also time their operation to the row cycle sync pulse.