DLPU125 june 2023
The Apps FPGA receives two externally sourced clocks as reference clocks for internal PLLs:
sysclk_p/n
from the VC-707 EVM, 200 MHz oscillatorusb_if_clk
from the Infineon - Cypress USB interface chipA third external clock source, spare_clk, driven from the DLPLCRC910EVM, is not used by the Apps FPGA. This clock is provided as both differential and single ended signal types.