DLPU125 june 2023
Register read word transactions are 3 clocks in length. Register data read transaction timing is shown in Register Data Read Transaction Timing Diagram.
The Apps FPGA GPIF supports multiple register read transactions from the previously written register address, without needing a new address transaction. This lowers the time overhead when polling a status register.
A
Register read word transaction example is shown in Register Data Read Transaction
Example and illustrates reading of register value 0x04030201
.
Signal | Idle | Start low word read | Read low word | Idle | Start high word read | Read high word | Idle |
---|---|---|---|---|---|---|---|
usb_if_clock |
2 clock cycles | 1 clock cycle | 2 clock cycles | 1 clock cycle | |||
usb_fd(15:8) |
0x00 | -- | 0x02 | 0x00 | -- | 0x04 | 0x00 |
usb_fd(7:0) |
0x00 | -- | 0x01 | 0x00 | -- | 0x03 | 0x00 |
usb_ctrl(2:0) |
Idle | Data read– “001” | Data read– “001” | Idle | Data read– “001” | Data read – “001” | Idle |