JAJS398F January   2009  – April 2018 DAC7568 , DAC8168 , DAC8568

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Electrical Characteristics
    3. 8.3 Timing Requirements
    4. 8.4 Typical Characteristics: Internal Reference
    5. 8.5 Typical Characteristics: DAC at AVDD = 5.5 V
    6. 8.6 Typical Characteristics: DAC at AVDD = 3.6 V
    7. 8.7 Typical Characteristics: DAC at AVDD = 2.7 V
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1  Digital-to-Analog Converter (DAC)
      2. 9.2.2  Resistor String
      3. 9.2.3  Output Amplifier
      4. 9.2.4  Internal Reference
      5. 9.2.5  Serial Interface
      6. 9.2.6  Input Shift Register
        1. Table 1. DAC8568 Data Input Register Format
        2. Table 2. DAC8168 Data Input Register Format
        3. Table 3. DAC7568 Data Input Register Format
      7. 9.2.7  SYNC Interrupt
      8. 9.2.8  Power-on Reset to Zero Scale or Midscale
      9. 9.2.9  Clear Code Register and CLR Pin
      10. 9.2.10 Software Reset Function
      11. 9.2.11 Operating Examples: DAC7568/DAC8168/DAC8568
        1. Table 4.   1st: Write to Data Buffer A:
        2. Table 5.   2nd: Write to Data Buffer B:
        3. Table 6.   3rd: Write to Data Buffer G:
        4. Table 7.   4th: Write to Data Buffer H and Simultaneously Update all DACs:
        5. Table 8.   1st: Write to Data Buffer C and Load DAC C: DAC C Output Settles to Specified Value Upon Completion:
        6. Table 9.   2nd: Write to Data Buffer D and Load DAC D: DAC D Output Settles to Specified Value Upon Completion:
        7. Table 10. 3rd: Write to Data Buffer E and Load DAC E: DAC E Output Settles to Specified Value Upon Completion:
        8. Table 11. 4th: Write to Data Buffer F and Load DAC F: DAC F Output Settles to Specified Value Upon Completion:
        9. Table 12. 1st: Write Power-Down Command to DAC Channel A and DAC Channel B: DAC A and DAC B to 1kΩ.
        10. Table 13. 2nd: Write Power-Down Command to DAC Channel H: DAC H to 1kΩ.
        11. Table 14. 3rd: Write Power-Down Command to DAC Channel C and DAC Channel D: DAC C and DAC D to 100kΩ.
        12. Table 15. 4th: Write Power-Down Command to DAC Channel F: DAC F to 100kΩ.
        13. Table 16. 1st: Write Sequence for Enabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time:
        14. Table 17. 2nd: Write Sequence to Power-Down All DACs to High-Impedance:
        15. Table 18. 1st: Write Sequence for Disabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time (after this sequence, these devices require an external reference source to function):
        16. Table 19. 2nd: Write Sequence to Write Specified Data to All DACs:
    3. 9.3 Device Functional Modes
      1. 9.3.1 Enable/Disable Internal Reference
        1. 9.3.1.1 Static Mode
          1. Table 20. Write Sequence for Enabling Internal Reference (Static Mode) (Internal Reference Powered On—08000001h)
          2. Table 21. Write Sequence for Disabling Internal Reference (Static Mode) (Internal Reference Powered On—08000000h)
        2. 9.3.1.2 Flexible Mode
          1. Table 22. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Powered On—09080000h)
          2. Table 23. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Always Powered On—090A0000h)
          3. Table 24. Write Sequence for Disabling Internal Reference (Flexible Mode) (Internal Reference Always Powered Down—090C0000h)
          4. Table 25. Write Sequence for Switching from Flexible Mode to Static Mode for Internal Reference (Internal Reference Always Powered Down—09000000h)
      2. 9.3.2 LDAC Functionality
      3. 9.3.3 Power-Down Modes
        1. 9.3.3.1 DAC Power-Down Commands
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications - Microprocessor Interfacing
      1. 10.2.1 DAC7568/DAC8168/DAC8568 to an 8051 Interface
        1. 10.2.1.1 Detailed Design Procedure
          1. 10.2.1.1.1 Internal Reference
            1. 10.2.1.1.1.1 Supply Voltage
            2. 10.2.1.1.1.2 Temperature Drift
            3. 10.2.1.1.1.3 Noise Performance
            4. 10.2.1.1.1.4 Load Regulation
            5. 10.2.1.1.1.5 Long-Term Stability
            6. 10.2.1.1.1.6 Thermal Hysteresis
          2. 10.2.1.1.2 DAC Noise Performance
          3. 10.2.1.1.3 Bipolar Operation Using The DAC7568/DAC8168/DAC8568
      2. 10.2.2 DAC7568/DAC8168/DAC8568 to Microwire Interface
      3. 10.2.3 DAC7568/DAC8168/DAC8568 to 68HC11 Interface
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの項目表記
        1. 12.1.1.1 静的特性
          1. 12.1.1.1.1  分解能
          2. 12.1.1.1.2  最下位ビット(LSB)
          3. 12.1.1.1.3  最上位ビット(MSB)
          4. 12.1.1.1.4  相対精度または積分非直線性(INL)
          5. 12.1.1.1.5  微分非直線性(DNL)
          6. 12.1.1.1.6  フルスケール誤差
          7. 12.1.1.1.7  オフセット誤差
          8. 12.1.1.1.8  ゼロ・コード誤差
          9. 12.1.1.1.9  ゲイン誤差
          10. 12.1.1.1.10 フルスケール誤差ドリフト
          11. 12.1.1.1.11 オフセット誤差ドリフト
          12. 12.1.1.1.12 ゼロ・コード誤差ドリフト
          13. 12.1.1.1.13 ゲイン温度係数
          14. 12.1.1.1.14 電源除去率(PSRR)
          15. 12.1.1.1.15 単調性
        2. 12.1.1.2 動的特性
          1. 12.1.1.2.1  スルー・レート
          2. 12.1.1.2.2  出力電圧のセトリング時間
          3. 12.1.1.2.3  コード変化/デジタル-アナログ・グリッチ・エネルギー
          4. 12.1.1.2.4  デジタル・フィードスルー
          5. 12.1.1.2.5  チャネル間DCクロストーク
          6. 12.1.1.2.6  チャネル間ACクロストーク
          7. 12.1.1.2.7  信号対雑音比(SNR)
          8. 12.1.1.2.8  全高調波歪み(THD)
          9. 12.1.1.2.9  スプリアスフリー・ダイナミック・レンジ(SFDR)
          10. 12.1.1.2.10 信号対雑音比+歪み(SINAD)
          11. 12.1.1.2.11 DAC出力ノイズ密度
          12. 12.1.1.2.12 DAC出力ノイズ
          13. 12.1.1.2.13 フルスケール範囲(FSR)
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

8.2 Electrical Characteristics

At AVDD = 2.7V to 5.5V and over –40°C to +125°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(1)
DAC8568 Resolution 16 Bits
Relative accuracy Measured by the line passing through codes 485 and 64714 ±4 ±12 LSB
Differential nonlinearity 16-bit monotonic ±0.2 ±1 LSB
DAC8168 Resolution 14 Bits
Relative accuracy Measured by the line passing through codes 120 and 16200 ±1 ±4 LSB
Differential nonlinearity 14-bit monotonic ±0.1 ±0.5 LSB
DAC7568 Resolution 12 Bits
Relative accuracy Measured by the line passing through codes 30 and 4050 ±0.3 ±1 LSB
Differential nonlinearity 12-bit monotonic ±0.05 ±0.25 LSB
Offset error Extrapolated from two-point line(1), unloaded ±1 ±4 mV
Offset error drift ±0.5 μV/°C
Full-scale error DAC register loaded with all '1's ±0.03 ±0.2 % of FSR
Zero-code error DAC register loaded with all '0's 1 4 mV
Zero-code error drift ±2 μV/°C
Gain error Extrapolated from two-point line(1), unloaded ±0.01 ±0.15 % of FSR
Gain temperature coefficient ±1 ppm of
FSR/°C
OUTPUT CHARACTERISTICS(2)
Output voltage range AVDD ≥ 2.7V; grades A and B: maximum output voltage 2.5V when using internal reference 0 AVDD V
AVDD ≥ 5V; grades C and D: maximum output voltage 5V when using internal reference
Output voltage settling time DACs unloaded; 1/4 scale to 3/4 scale to ±0.024% 5 10 μs
RL = 1MΩ 10
Slew rate 0.75 V/μs
Capacitive load stability RL = ∞ 1000 pF
RL = 2kΩ 3000
Code change glitch impulse 1LSB change around major carry 0.1 nV-s
Digital feedthrough SCLK toggling, SYNC high 0.1 nV-s
Power-on glitch impulse RL = 2kΩ, CL = 470pF, AVDD = 5.5V 10 mV
RL = 2kΩ, CL = 470pF, AVDD = 2.7V 6 mV
Channel-to-channel dc crosstalk Full-scale swing on adjacent channel 0.1 LSB
Channel-to-channel ac crosstalk RL = 2kΩ, CL = 420pF, 1kHz full-scale sine wave, outputs unloaded –109 dB
DC output impedance At mid-code input 4 Ω
Short-circuit current DAC outputs at full-scale, DAC outputs shorted to GND 11 mA
Power-up time, including settling time Coming out of power-down mode 50 μs
AC PERFORMANCE(2)
SNR TA = +25°C, BW = 20kHz, AVDD = 5V, fOUT = 1kHz,
first 19 harmonics removed for SNR calculation,
at 16-bit level		 83 dB
THD –63 dB
SFDR 63 dB
SINAD 62 dB
DAC output noise density TA = +25°C, at zero-code input, fOUT = 1kHz 90 nV/√Hz
DAC output noise TA = +25°C, at mid-code input, 0.1Hz to 10Hz 2.6 μVPP
REFERENCE
Internal reference current consumption AVDD = 5.5V 360 μA
AVDD = 3.6V 348 μA
External reference current External VREF = 2.5V (when internal reference is disabled), all eight channels active Grades A/B 60 μA
Grades C/D 115
VREFIN Reference input range Grades A/B, AVDD = 2.7V to 5.5V 0 AVDD V
Grades C/D, AVDD = 5.0V to 5.5V 0 AVDD/2 V
Reference input impedance Grades A/B 44 kΩ
Grades C/D 22
REFERENCE OUTPUT
Output voltage TA = +25°C; all grades 2.4975 2.5 2.5025 V
Initial accuracy TA = +25°C, all grades –0.1 ±0.004 0.1 %
Output voltage temperature drift DAC7568/DAC8168/DAC8568(3),grades A/B 5 25 ppm/°C
DAC7568/DAC8168/DAC8568(4), grades C/D 2 5
Output voltage noise f = 0.1Hz to 10Hz 12 μVPP
Output voltage noise density
(high-frequency noise)		 TA = +25°C, f = 1MHz, CL = 0μF 50 nV/√Hz
TA = +25°C, f = 1MHz, CL = 1μF 20
TA = +25°C, f = 1MHz, CL = 4μF 16
Load regulation, sourcing(5) TA = +25°C 30 μV/mA
Load regulation, sinking(5) TA = +25°C 15 μV/mA
Output current load capability(2) ±20 mA
Line regulation TA = +25°C 10 μV/V
Long-term stability/drift (aging)(5) TA = +25°C, time = 0 to 1900 hours 50 ppm
Thermal hysteresis(5) First cycle 100 ppm
Additional cycles 25
LOGIC INPUTS(2)
Input current ±1 μA
VINL Logic input LOW voltage 2.7V ≤ AVDD ≤ 5.5V 0.3 × AVDD V
VINH Logic input HIGH voltage 2.7V ≤ AVDD < 4.5V 0.7 × AVDD V
4.5V ≤ AVDD ≤ 5.5V 0.625 × AVDD V
Pin capacitance 3 pF
POWER REQUIREMENTS
AVDD 2.7 5.5 V
IDD(6) Normal mode, internal reference switched off AVDD = 3.6V to 5.5V
VINH = AVDD and VINL = GND		 0.95 1.4 mA
AVDD = 2.7V to 3.6V
VINH = AVDD and VINL = GND		 0.81 1.3
Normal mode, internal reference switched on AVDD = 3.6V to 5.5V
VINH = AVDD and VINL = GND		 1.25 2.5 mA
AVDD = 2.7V to 3.6V
VINH = AVDD and VINL = GND		 1.1 1.9
All power-down modes AVDD = 3.6V to 5.5V
VINH = AVDD and VINL = GND		 0.18 3 μA
AVDD = 2.7V to 3.6V
VINH = AVDD and VINL = GND		 0.10 2.5
Power dissipation(6) Normal mode, internal reference switched off AVDD = 3.6V to 5.5V
VINH = AVDD and VINL = GND		 3.4 7.7 mW
AVDD = 2.7V to 3.6V
VINH = AVDD and VINL = GND		 2.2 4.7
Normal mode, internal reference switched on AVDD = 3.6V to 5.5V
VINH = AVDD and VINL = GND		 4.5 11 mW
AVDD = 2.7V to 3.6V
VINH = AVDD and VINL = GND		 2.9 6.8
All power-down modes AVDD = 3.6V to 5.5V
VINH = AVDD and VINL = GND		 0.6 16 μW
AVDD = 2.7V to 3.6V
VINH = AVDD and VINL = GND		 0.3 9
TEMPERATURE RANGE
Specified performance –40 +125 °C
(1) 16-bit: codes 485 and 64714; 14-bit: codes 120 and 16200; 12-bit: codes 30 and 4050
(2) Specified by design or characterization; not production tested.
(3) Reference is trimmed and tested at room temperature, and is characterized from –40°C to +125°C.
(4) Reference is trimmed and tested at two temperatures (+25°C and +105°C), and is characterized from –40°C to +125°C.
(5) Explained in more detail in the Application Information section of this data sheet.
(6) Input code = midscale, no load.