JAJSHX5F October   2010  – September 2019 ADS1118

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      K タイプの熱電対測定 内蔵温度センサによる冷接点補償
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements: Serial Interface
    7. 8.7 Switching Characteristics: Serial Interface
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Noise Performance
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Multiplexer
      2. 10.3.2 Analog Inputs
      3. 10.3.3 Full-Scale Range (FSR) and LSB Size
      4. 10.3.4 Voltage Reference
      5. 10.3.5 Oscillator
      6. 10.3.6 Temperature Sensor
        1. 10.3.6.1 Converting from Temperature to Digital Codes
        2. 10.3.6.2 Converting from Digital Codes to Temperature
    4. 10.4 Device Functional Modes
      1. 10.4.1 Reset and Power Up
      2. 10.4.2 Operating Modes
        1. 10.4.2.1 Single-Shot Mode and Power-Down
        2. 10.4.2.2 Continuous-Conversion Mode
      3. 10.4.3 Duty Cycling for Low Power
    5. 10.5 Programming
      1. 10.5.1 Serial Interface
      2. 10.5.2 Chip Select (CS)
      3. 10.5.3 Serial Clock (SCLK)
      4. 10.5.4 Data Input (DIN)
      5. 10.5.5 Data Output and Data Ready (DOUT/DRDY)
      6. 10.5.6 Data Format
      7. 10.5.7 Data Retrieval
        1. 10.5.7.1 32-Bit Data Transmission Cycle
        2. 10.5.7.2 16-Bit Data Transmission Cycle
    6. 10.6 Register Maps
      1. 10.6.1 Conversion Register [reset = 0000h]
        1. Table 6. Conversion Register Field Descriptions
      2. 10.6.2 Config Register [reset = 058Bh]
        1. Table 7. Config Register Field Descriptions
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Serial Interface Connections
      2. 11.1.2 GPIO Ports for Communication
      3. 11.1.3 Analog Input Filtering
      4. 11.1.4 Single-Ended Inputs
      5. 11.1.5 Connecting Multiple Devices
      6. 11.1.6 Pseudo Code Example
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
    1. 12.1 Power-Supply Sequencing
    2. 12.2 Power-Supply Decoupling
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 ドキュメントのサポート
      1. 14.1.1 関連資料
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報

9.1 Noise Performance

Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between modulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and thus reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the input-referred noise drops when reducing the output data rate because more samples of the internal modulator are averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is particularly useful when measuring low-level signals.

Table 1 and Table 2 summarize the device noise performance. Data are representative of typical noise performance at TA = 25°C with the inputs shorted together externally. Table 1 show the input-referred noise in units of μVRMS for the conditions shown. Note that µVPP values are shown in parenthesis. Table 2 shows the corresponding data in effective number of bits (ENOB) calculated from μVRMS values using Equation 1. The noise-free bits calculated from peak-to-peak noise values using Equation 2 are shown in parenthesis.

Equation 1. ENOB = ln (FSR / VRMS-Noise) / ln(2)
Equation 2. Noise-Free Bits = ln (FSR / VPP-Noise) / ln(2)

Table 1. Noise in μVRMS (μVPP) at VDD = 3.3 V

DATA RATE
(SPS)		 FSR (Full-Scale Range)
±6.144 V ±4.096 V ±2.048 V ±1.024 V ±0.512 V ±0.256 V
8 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)
16 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)
32 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)
64 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (7.81)
128 187.5 (187.5) 125 (125) 62.5 (62.5) 31.25 (31.25) 15.62 (15.62) 7.81 (12.35)
250 187.5 (252.09) 125 (148.28) 62.5 (84.03) 31.25 (39.54) 15.62 (16.06) 7.81 (18.53)
475 187.5 (266.92) 125 (227.38) 62.5 (79.08) 31.25 (56.84) 15.62 (32.13) 7.81 (25.95)
860 187.5 (430.06) 125 (266.93) 62.5 (118.63) 31.25 (64.26) 15.62 (40.78) 7.81 (35.83)

Table 2. ENOB from RMS Noise (Noise-Free Bits from Peak-to-Peak Noise) at VDD = 3.3 V

DATA RATE
(SPS)		 FSR (Full-Scale Range)
±6.144 V ±4.096 V ±2.048 V ±1.024 V ±0.512 V ±0.256 V
8 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
16 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
32 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
64 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
128 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.33)
250 16 (15.57) 16 (15.75) 16 (15.57) 16 (15.66) 16 (15.96) 16 (14.75)
475 16 (15.49) 16 (15.13) 16 (15.66) 16 (15.13) 16 (14.95) 16 (14.26)
860 16 (14.8) 16 (14.9) 16 (15.07) 16 (14.95) 16 (14.61) 16 (13.8)