SBAA381A April   2019  – January 2024 TLV320ADC3140 , TLV320ADC5140 , TLV320ADC6140

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Processing Blocks of TLV320ADCx140/PCMx140-Q1
    1. 2.1 Decimation Filter Response
      1. 2.1.1 Supported Sample Rates
    2. 2.2 AGC or DRE
      1. 2.2.1 Supported Sample Rates
      2. 2.2.2 Channel Assignment
    3. 2.3 Channel Summer, Digital Mixer, and Bi-quads
  6. 3Processing Blocks Supported for Different Sample Rates
    1. 3.1 8 kHz Sample Rate
    2. 3.2 16 kHz-48 kHz Sample Rate
    3. 3.3 96 kHz Sample Rate
    4. 3.4 192 kHz Sample Rate
    5. 3.5 384 kHz Sample Rate
    6. 3.6 768 kHz Sample Rate
  7. 4Example Configurations
  8. 5References
  9.   Revision History

2.2 AGC or DRE

Analog channels include two additional processing blocks:

  • Automatic Gain Control (AGC) is an algorithm that dynamically controls the gain of the ADC channel to maintain a nominally constant output level. AGC is available on all TLV320ADCx140/PCMx140-Q1 device variants.
  • Dynamic Range Enhancer (DRE) is an algorithm that dynamically adjusts the PGA gain of the ADC channel to enhance the dynamic range. DRE is available on the TLV320ADC5140 and TLV320AD6140 devices.

Only one of these blocks can be enabled at a time. These blocks are enabled by setting the DRE_AGC_SEL bit in DSP_CFG1 (P0_R108_D[3]) to 1. Table 2-3 shows the AGC_SEL definition.

Table 2-3 AGC Selection Register Field Description
P0_R106_D[3] : AGC_SEL[1:0]AGC or DRE SELECTION
0 (default)AGC is not selected (DRE is selected for TLV320ADC5140 and TLV320ADC6140).
1AGC is selected (DRE is not selected).