SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
Table 7-4 lists the memory-mapped registers for the flash memory controller.
Address | Acronym | Register Name | Type | Reset | Section |
---|---|---|---|---|---|
128h | FCTL1 | Flash memory control 1 | Read/write | 9600h with PUC | Section 7.5.1 |
12Ah | FCTL2 | Flash memory control 2 | Read/write | 9642h with PUC | Section 7.5.2 |
12Ch | FCTL3 | Flash memory control 3 | Read/write | 9658h with PUC#SLAU144FCTL83 | Section 7.5.3 |
1BEh | FCTL4#SLAU144FCTL9209 | Flash memory control 4 | Read/write | 00h with PUC | Section 7.5.4 |
0h | IE1 | Interrupt enable 1 | Read/write | 00h with PUC | Section 7.5.5 |
Flash Memory Control 1 Register
FCTL1 is shown in Figure 7-13 and described in Table 7-5.
Return to Table 7-4.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FRKEY FWKEY | |||||||
rw-1 | rw-0 | rw-0 | rw-1 | rw-0 | rw-1 | rw-1 | rw-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BLKWRT | WRT | Reserved | EEIEX#SLAU144FCTL1858 | EEI#SLAU144FCTL1858 | MERAS | ERASE | Reserved |
rw-0 | rw-0 | r0 | rw-0 | rw-0 | rw-0 | rw-0 | r0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | FRKEY FWKEY | R/W | 96h | FCTLx password. Always reads as 096h. Must be written as 0A5h. Writing any other value generates a PUC. |
7 | BLKWRT | R/W | 0h | Block write mode. WRT must also be set for block write mode. BLKWRT is automatically reset when EMEX is set. 0b = Block-write mode is off 1b = Block-write mode is on |
6 | WRT | R/W | 0h | Write. This bit is used to select any write mode. WRT is automatically reset when EMEX is set. 0b = Write mode is off 1b = Write mode is on |
5 | Reserved | R | 0h | |
4 | EEIEX | R/W | 0h | Enable emergency interrupt exit. Setting this bit enables an interrupt to cause an emergency exit from a flash operation when GIE = 1. EEIEX is automatically reset when EMEX is set. Not present on MSP430x20xx and MSP430G2xx devices. 0b = Exit interrupt disabled. 1b = Exit on interrupt enabled. |
3 | EEI | R/W | 0h | Enable erase interrupts. Setting this bit allows a segment erase to be interrupted by an interrupt request. After the interrupt is serviced the erase cycle is resumed. Not present on MSP430x20xx and MSP430G2xx devices. 0b = Interrupts during segment erase disabled. 1b = Interrupts during segment erase enabled. |
2 | MERAS | R/W | 0h | Mass erase and erase. These bits are used together to select the erase mode. MERAS and ERASE are automatically reset when EMEX is set. See Table 7-6. |
1 | ERASE | R/W | 0h | |
0 | Reserved | R | 0h |
MERAS | ERASE | Erase Cycle |
---|---|---|
0 | 0 | No erase |
0 | 1 | Erase individual segment only |
1 | 0 | Erase all main memory segments |
1 | 1 | LOCKA = 0: Erase main and information flash memory. LOCKA = 1: Erase only main flash memory. |
Flash Memory Control 2 Register
FCTL2 is shown in Figure 7-14 and described in Table 7-7.
Return to Table 7-4.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FWKEYx | |||||||
rw-1 | rw-0 | rw-0 | rw-1 | rw-0 | rw-1 | rw-1 | rw-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FSSELx | FNx | ||||||
rw-0 | rw-1 | rw-0 | rw-0 | rw-0 | rw-0 | rw-1 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | FWKEYx | R/W | 96h | FCTLx password. Always reads as 096h. Must be written as 0A5h. Writing any other value generates a PUC. |
7-6 | FSSELx | R/W | 1h | Flash controller clock source select 00b = ACLK 01b = MCLK 10b = SMCLK 11b = SMCLK |
5-0 | FNx | R/W | 2h | Flash controller clock divider. These six bits select the divider for the flash controller clock. The divisor value is FNx + 1. For example, when FNx = 00h, the divisor is 1. When FNx = 03Fh, the divisor is 64. |
Flash Memory Control 3 Register
FCTL3 is shown in Figure 7-15 and described in Table 7-8.
Return to Table 7-4.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FWKEYx | |||||||
rw-1 | rw-0 | rw-0 | rw-1 | rw-0 | rw-1 | rw-1 | rw-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FAIL | LOCKA | EMEX | LOCK | WAIT | ACCVIFG | KEYV | BUSY |
r(w)-0 | r(w)-1 | rw-0 | rw-1 | r-1 | rw-0 | rw-(0) | r-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | FWKEYx | R/W | 96h | FCTLx password. Always reads as 096h. Must be written as 0A5h. Writing any other value generates a PUC. |
7 | FAIL | R/W | 0h | Operation failure. This bit is set if the fFTG clock source fails, or a flash operation is aborted from an interrupt when EEIEX = 1. FAIL must be reset with software. 0b = No failure 1b = Failure |
6 | LOCKA | R/W | 1h | Segment A and Info lock. Write a 1 to this bit to change its state. Writing 0 has no effect. 0b = Segment A unlocked and all information memory is erased during a mass erase. 1b = Segment A locked and all information memory is protected from erasure during a mass erase. |
5 | EMEX | R/W | 0h | Emergency exit 0b = No emergency exit 1b = Emergency exit |
4 | LOCK | R/W | 1h | Lock. This bit unlocks the flash memory for writing or erasing. The LOCK bit can be set any time during a byte or word write or erase operation, and the operation completes normally. In the block write mode if the LOCK bit is set while BLKWRT = WAIT = 1, then BLKWRT and WAIT are reset and the mode ends normally. 0b = Unlocked 1b = Locked |
3 | WAIT | R | 1h | Wait. Indicates the flash memory is being written to. 0b = The flash memory is not ready for the next byte or word write 1b = The flash memory is ready for the next byte or word write |
2 | ACCVIFG | R/W | 0h | Access violation interrupt flag 0b = No interrupt pending 1b = Interrupt pending |
1 | KEYV | R/W | 0h | Flash security key violation. This bit indicates an incorrect FCTLx password was written to any flash control register and generates a PUC when set. KEYV must be reset with software. KEYV is reset with POR. 0b = FCTLx password was written correctly 1b = FCTLx password was written incorrectly |
0 | BUSY | R | 0h | Busy. This bit indicates the status of the flash timing generator. 0b = Not busy 1b = Busy |
Flash Memory Control 4 Register. This register is not available in all devices. See the device-specific data sheet for details.
FCTL4 is shown in Figure 7-16 and described in Table 7-9.
Return to Table 7-4.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FWKEYx | |||||||
rw-1 | rw-0 | rw-0 | rw-1 | rw-0 | rw-1 | rw-1 | rw-0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | MRG1 | MRG0 | Reserved | ||||
r-0 | r-0 | rw-0 | rw-0 | r-0 | r-0 | r-0 | r-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | FWKEYx | R/W | 96h | FCTLx password. Always reads as 096h. Must be written as 0A5h. Writing any other value generates a PUC. |
7-6 | Reserved | R | 0h | Reserved. Always read as 0. |
5 | MRG1 | R/W | 0h | Marginal read 1 mode. This bit enables the marginal 1 read mode. The marginal read 1 bit is cleared if the CPU starts execution from the flash memory. If both MRG1 and MRG0 are set, MRG1 is active and MRG0 is ignored. 0b = Marginal 1 read mode is disabled. 1b = Marginal 1 read mode is enabled. |
4 | MRG0 | R/W | 0h | Marginal read 0 mode. This bit enables the marginal 0 read mode. The marginal mode 0 is cleared if the CPU starts execution from the flash memory. If both MRG1 and MRG0 are set, MRG1 is active and MRG0 is ignored. 0b = Marginal 0 read mode is disabled. 1b = Marginal 0 read mode is enabled. |
3-0 | Reserved | R | 0h | Reserved. Always read as 0. |
Interrupt Enable 1 Register
IE1 is shown in Figure 7-17 and described in Table 7-10.
Return to Table 7-4.
Reset with PUC.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACCVIE | |||||||
rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | These bits may be used by other modules. See the device-specific data sheet. | |||
5 | ACCVIE | R/W | 0h | Flash memory access violation interrupt enable. This bit enables the ACCVIFG interrupt. Because other bits in IE1 may be used for other modules, Ti recommends setting or clearing this bit using BIS.B or BIC.B instructions, respectively, rather than MOV.B or CLR.B instructions. 0b = Interrupt not enabled 1b = Interrupt enabled |
4-0 | These bits may be used by other modules. See the device-specific data sheet. |