SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
Table 15-6 lists the memory-mapped registers for USCI_A0 and USCI_A1 in UART mode.
Address | Acronym | Register Name | Type | Reset | Section |
---|---|---|---|---|---|
60h | UCA0CTL0 | USCI_A0 control 0 | Read/write | 00h with PUC | Section 15.5.1 |
61h | UCA0CTL1 | USCI_A0 control 1 | Read/write | 01h with PUC | Section 15.5.2 |
62h | UCA0BR0 | USCI_A0 baud-rate control 0 | Read/write | 00h with PUC | Section 15.5.3 |
63h | UCA0BR1 | USCI_A0 baud-rate control 1 | Read/write | 00h with PUC | Section 15.5.3 |
64h | UCA0MCTL | USCI_A0 modulation control | Read/write | 00h with PUC | Section 15.5.5 |
65h | UCA0STAT | USCI_A0 status | Read/write | 00h with PUC | Section 15.5.6 |
66h | UCA0RXBUF | USCI_A0 receive buffer | Read | 00h with PUC | Section 15.5.7 |
67h | UCA0TXBUF | USCI_A0 transmit buffer | Read/write | 00h with PUC | Section 15.5.8 |
5Dh | UCA0ABCTL | USCI_A0 auto baud control | Read/write | 00h with PUC | Section 15.5.11 |
5Eh | UCA0IRTCTL | USCI_A0 IrDA transmit control | Read/write | 00h with PUC | Section 15.5.9 |
5Fh | UCA0IRRCTL | USCI_A0 IrDA receive control | Read/write | 00h with PUC | Section 15.5.10 |
1h | IE2 | SFR interrupt enable 2 | Read/write | 00h with PUC | Section 15.5.12 |
3h | IFG2 | SFR interrupt flag 2 | Read/write | 0Ah with PUC | Section 15.5.13 |
D0h | UCA1CTL0 | USCI_A1 control 0 | Read/write | 00h with PUC | Section 15.5.1 |
D1h | UCA1CTL1 | USCI_A1 control 1 | Read/write | 01h with PUC | Section 15.5.2 |
D2h | UCA1BR0 | USCI_A1 baud-rate control 0 | Read/write | 00h with PUC | Section 15.5.3 |
D3h | UCA1BR1 | USCI_A1 baud-rate control 1 | Read/write | 00h with PUC | Section 15.5.3 |
D4h | UCA1MCTL | USCI_A1 modulation control | Read/write | 00h with PUC | Section 15.5.5 |
D5h | UCA1STAT | USCI_A1 status | Read/write | 00h with PUC | Section 15.5.6 |
D6h | UCA1RXBUF | USCI_A1 receive buffer | Read | 00h with PUC | Section 15.5.7 |
D7h | UCA1TXBUF | USCI_A1 transmit buffer | Read/write | 00h with PUC | Section 15.5.8 |
CDh | UCA1ABCTL | USCI_A1 auto baud control | Read/write | 00h with PUC | Section 15.5.11 |
CEh | UCA1IRTCTL | USCI_A1 IrDA transmit control | Read/write | 00h with PUC | Section 15.5.9 |
CFh | UCA1IRRTCTL | USCI_A1 IrDA receive control | Read/write | 00h with PUC | Section 15.5.10 |
6h | UC1IE | USCI_A1/B1 interrupt enable | Read/write | 00h with PUC | Section 15.5.14 |
7h | UC1IFG | USCI_A1/B1 interrupt flag | Read/write | 0Ah with PUC | Section 15.5.15 |
Modifying SFR bits
To avoid modifying control bits of other modules, TI recommends setting or clearing the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
USCI_Ax Control 0 Register
UCAxCTL0 is shown in Figure 15-12 and described in Table 15-7.
Return to Table 15-6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCPEN | UCPAR | UCMSB | UC7BIT | UCSPB | UCMODEx | UCSYNC | |
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | UCPEN | R/W | 0h | Parity enable 0b = Parity disabled 1b = Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. |
6 | UCPAR | R/W | 0h | Parity select. UCPAR is not used when parity is disabled. 0b = Odd parity 1b = Even parity |
5 | UCMSB | R/W | 0h | MSB first select. Controls the direction of the receive and transmit shift register. 0b = LSB first 1b = MSB first |
4 | UC7BIT | R/W | 0h | Character length. Selects 7-bit or 8-bit character length. 0b = 8-bit data 1b = 7-bit data |
3 | UCSPB | R/W | 0h | Stop bit select. Number of stop bits. 0b = One stop bit 1b = Two stop bits |
2-1 | UCMODEx | R/W | 0h | USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0. 00b = UART mode 01b = Idle-line multiprocessor mode 10b = Address-bit multiprocessor mode 11b = UART mode with automatic baud rate detection |
0 | UCSYNC | R/W | 0h | Synchronous mode enable 0b = Asynchronous mode 1b = Synchronous mode |
USCI_Ax Control 1 Register
UCAxCTL1 is shown in Figure 15-13 and described in Table 15-8.
Return to Table 15-6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCSSELx | UCRXEIE | UCBRKIE | UCDORM | UCTXADDR | UCTXBRK | UCSWRST | |
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | UCSSELx | R/W | 0h | USCI clock source select. These bits select the BRCLK source clock. 00b = UCLK 01b = ACLK 10b = SMCLK 11b = SMCLK |
5 | UCRXEIE | R/W | 0h | Receive erroneous-character interrupt-enable 0b = Erroneous characters rejected and UCAxRXIFG is not set 1b = Erroneous characters received will set UCAxRXIFG |
4 | UCBRKIE | R/W | 0h | Receive break character interrupt-enable 0b = Received break characters do not set UCAxRXIFG. 1b = Received break characters set UCAxRXIFG. |
3 | UCDORM | R/W | 0h | Dormant. Puts USCI into sleep mode. 0b = Not dormant. All received characters will set UCAxRXIFG. 1b = Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG. |
2 | UCTXADDR | R/W | 0h | Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode. 0b = Next frame transmitted is data 1b = Next frame transmitted is an address |
1 | UCTXBRK | R/W | 0h | Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer. 0b = Next frame transmitted is not a break 1b = Next frame transmitted is a break or a break/synch |
0 | UCSWRST | R/W | 1h | Software reset enable 0b = Disabled. USCI reset released for operation. 1b = Enabled. USCI logic held in reset state. |
USCI_Ax Baud-Rate Control 0 Register
UCAxBR0 is shown in Figure 15-14 and described in Table 15-9.
Return to Table 15-6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCBR0 | |||||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UCBR0 | R/W | 0h | Clock prescaler setting of the baud-rate generator. The 16-bit value of (UCAxBR0 + UCAxBR1 × 256) forms the prescaler value. |
USCI_Ax Baud-Rate Control 1 Register
UCAxBR1 is shown in Figure 15-14 and described in Table 15-9.
Return to Table 15-6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCBR1 | |||||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UCBR1 | R/W | 0h | Clock prescaler setting of the baud-rate generator. The 16-bit value of (UCAxBR0 + UCAxBR1 × 256) forms the prescaler value. |
USCI_Ax Modulation Control Register
UCAxMCTL is shown in Figure 15-16 and described in Table 15-11.
Return to Table 15-6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCBRFx | UCBRSx | UCOS16 | |||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | UCBRFx | R/W | 0h | First modulation stage select. These bits determine the modulation pattern for BITCLK16 when UCOS16 = 1. Ignored with UCOS16 = 0. Table 15-3 shows the modulation pattern. |
3-1 | UCBRSx | R/W | 0h | Second modulation stage select. These bits determine the modulation pattern for BITCLK. Table 15-2 shows the modulation pattern. |
0 | UCOS16 | R/W | 0h | Oversampling mode enabled 0b = Disabled 1b = Enabled |
USCI_Ax Status Register
UCAxSTAT is shown in Figure 15-17 and described in Table 15-12.
Return to Table 15-6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCLISTEN | UCFE | UCOE | UCPE | UCBRK | UCRXERR | UCADDR UCIDLE | UCBUSY |
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | r-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | UCLISTEN | R/W | 0h | Listen enable. The UCLISTEN bit selects loopback mode. 0b = Disabled 1b = Enabled. UCAxTXD is internally fed back to the receiver. |
6 | UCFE | R/W | 0h | Framing error flag 0b = No error 1b = Character received with low stop bit |
5 | UCOE | R/W | 0h | Overrun error flag. This bit is set when a character is transferred into UCAxRXBUF before the previous character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by software. Otherwise, it will not function correctly. 0b = No error 1b = Overrun error occurred |
4 | UCPE | R/W | 0h | Parity error flag. When UCPEN = 0, UCPE is read as 0. 0b = No error 1b = Character received with parity error |
3 | UCBRK | R/W | 0h | Break detect flag 0b = No break condition 1b = Break condition occurred |
2 | UCRXERR | R/W | 0h | Receive error flag. This bit indicates a character was received with errors. When UCRXERR = 1, one or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read. 0b = No receive errors detected 1b = Receive error detected |
1 | UCADDR UCIDLE | R/W | 0h | UCADDR: Address received in address-bit multiprocessor mode. 0b = Received character is data 1b = Received character is an address UCIDLE: Idle line detected in idle-line multiprocessor mode. 0b = No idle line detected 1b = Idle line detected |
0 | UCBUSY | R | 0h | USCI busy. This bit indicates if a transmit or receive operation is in progress. 0b = USCI inactive 1b = USCI transmitting or receiving |
USCI_Ax Receive Buffer Register
UCAxRXBUF is shown in Figure 15-18 and described in Table 15-13.
Return to Table 15-6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCRXBUFx | |||||||
r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | r-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UCRXBUFx | R | 0h | The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UCAxRXBUF resets the receive-error bits, the UCADDR or UCIDLE bit, and UCAxRXIFG. In 7-bit data mode, UCAxRXBUF is LSB justified and the MSB is always reset. |
USCI_Ax Transmit Buffer Register
UCAxTXBUF is shown in Figure 15-19 and described in Table 15-14.
Return to Table 15-6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCTXBUFx | |||||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UCTXBUFx | R/W | 0h | The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted on UCAxTXD. Writing to the transmit data buffer clears UCAxTXIFG. The MSB of UCAxTXBUF is not used for 7-bit data and is reset. |
USCI_Ax IrDA Transmit Control Register
UCAxIRTCTL is shown in Figure 15-20 and described in Table 15-15.
Return to Table 15-6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCIRTXPLx | UCIRTXCLK | UCIREN | |||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | UCIRTXPLx | R/W | 0h | Transmit pulse length. Pulse length tPULSE = (UCIRTXPLx + 1) / (2 × fIRTXCLK) |
1 | UCIRTXCLK | R/W | 0h | IrDA transmit pulse clock select 0b = BRCLK 1b = BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. |
0 | UCIREN | R/W | 0h | IrDA encoder/decoder enable 0b = IrDA encoder/decoder disabled 1b = IrDA encoder/decoder enabled |
USCI_Ax IrDA Receive Control Register
UCAxIRRCTL is shown in Figure 15-21 and described in Table 15-16.
Return to Table 15-6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCIRRXFLx | UCIRRXPL | UCIRRXFE | |||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | UCIRRXFLx | R/W | 0h | Receive filter length. The minimum pulse length for receive is given by: tMIN = (UCIRRXFLx + 4) / (2 × fBRCLK) |
1 | UCIRRXPL | R/W | 0h | IrDA receive input UCAxRXD polarity 0b = IrDA transceiver delivers a high pulse when a light pulse is seen 1b = IrDA transceiver delivers a low pulse when a light pulse is seen |
0 | UCIRRXFE | R/W | 0h | IrDA receive filter enabled 0b = Receive filter disabled 1b = Receive filter enabled |
USCI_Ax Auto Baud Control Register
UCAxABCTL is shown in Figure 15-22 and described in Table 15-17.
Return to Table 15-6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | UCDELIMx | UCSTOE | UCBTOE | Reserved | UCABDEN | ||
r-0 | r-0 | rw-0 | rw-0 | rw-0 | rw-0 | r-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | Reserved | R | 0h | |
5-4 | UCDELIMx | R/W | 0h | Break and synch delimiter length 00b = 1 bit time 01b = 2 bit times 10b = 3 bit times 11b = 4 bit times |
3 | UCSTOE | R/W | 0h | Synch field time-out error 0b = No error 1b = Length of synch field exceeded measurable time. |
2 | UCBTOE | R/W | 0h | Break time-out error 0b = No error 1b = Length of break field exceeded 22 bit times. |
1 | Reserved | R | 0h | |
0 | UCABDEN | R/W | 0h | Automatic baud rate detect enable 0b = Baud rate detection disabled. Length of break and synch field is not measured. 1b = Baud rate detection enabled. Length of break and synch field is measured and baud rate settings are changed accordingly. |
SFR Interrupt Enable 2 Register
IE2 is shown in Figure 15-23 and described in Table 15-18.
Return to Table 15-6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCA0TXIE | UCA0RXIE | ||||||
rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | These bits may be used by other modules (see the device-specific data sheet). | |||
1 | UCA0TXIE | R/W | 0h | USCI_A0 transmit interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
0 | UCA0RXIE | R/W | 0h | USCI_A0 receive interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
SFR Interrupt Flag 2 Register
IFG2 is shown in Figure 15-24 and described in Table 15-19.
Return to Table 15-6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCA0TXIFG | UCA0RXIFG | ||||||
rw-1 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | These bits may be used by other modules (see the device-specific data sheet). | |||
1 | UCA0TXIFG | R/W | 0h | USCI_A0 transmit interrupt flag. UCA0TXIFG is set when UCA0TXBUF is empty. 0b = No interrupt pending 1b = Interrupt pending |
0 | UCA0RXIFG | R/W | 0h | USCI_A0 receive interrupt flag. UCA0RXIFG is set when UCA0RXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending |
USCI Interrupt Enable Register
UC1IE is shown in Figure 15-25 and described in Table 15-20.
Return to Table 15-6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Unused | UCA1TXIE | UCA1RXIE | |||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | Unused | R/W | 0h | Unused |
3-2 | These bits may be used by other USCI modules (see the device-specific data sheet). | |||
1 | UCA1TXIE | R/W | 0h | USCI_A1 transmit interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
0 | UCA1RXIE | R/W | 0h | USCI_A1 receive interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
USCI Interrupt Flag Register
UC1IFG is shown in Figure 15-26 and described in Table 15-21.
Return to Table 15-6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Unused | UCA1TXIFG | UCA1RXIFG | |||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-1 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | Unused | R/W | 0h | Unused |
3-2 | These bits may be used by other USCI modules (see the device-specific data sheet). | |||
1 | UCA1TXIFG | R/W | 0h | USCI_A1 transmit interrupt flag. UCA1TXIFG is set when UCA1TXBUF is empty. 0b = No interrupt pending 1b = Interrupt pending |
0 | UCA1RXIFG | R/W | 0h | USCI_A1 receive interrupt flag. UCA1RXIFG is set when UCA1RXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending |