SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
Table 16-2 lists the memory-mapped registers for USCI_Ax and USCI_Bx in SPI mode.
Address | Acronym | Register Name | Type | Reset | Section |
---|---|---|---|---|---|
60h | UCA0CTL0 | USCI_A0 control 0 | Read/write | 00h with PUC | Section 16.5.1 |
61h | UCA0CTL1 | USCI_A0 control 1 | Read/write | 01h with PUC | Section 16.5.2 |
62h | UCA0BR0 | USCI_A0 baud-rate control 0 | Read/write | 00h with PUC | Section 16.5.3 |
63h | UCA0BR1 | USCI_A0 baud-rate control 1 | Read/write | 00h with PUC | Section 16.5.3 |
65h | UCA0STAT | USCI_A0 status | Read/write | 00h with PUC | Section 16.5.5 |
66h | UCA0RXBUF | USCI_A0 receive buffer | Read | 00h with PUC | Section 16.5.6 |
67h | UCA0TXBUF | USCI_A0 transmit buffer | Read/write | 00h with PUC | Section 16.5.7 |
68h | UCB0CTL0 | USCI_B0 control 0 | Read/write | 01h with PUC | Section 16.5.1 |
69h | UCB0CTL1 | USCI_B0 control 1 | Read/write | 01h with PUC | Section 16.5.1 |
6Ah | UCB0BR0 | USCI_B0 bit-rate control 0 | Read/write | 00h with PUC | Section 16.5.3 |
6Bh | UCB0BR1 | USCI_B0 bit-rate control 1 | Read/write | 00h with PUC | Section 16.5.3 |
6Dh | UCB0STAT | USCI_B0 status | Read/write | 00h with PUC | Section 16.5.5 |
6Eh | UCB0RXBUF | USCI_B0 receive buffer | Read | 00h with PUC | Section 16.5.6 |
6Fh | UCB0TXBUF | USCI_B0 transmit buffer | Read/write | 00h with PUC | Section 16.5.7 |
1h | IE2 | SFR interrupt enable 2 | Read/write | 00h with PUC | Section 16.5.8 |
3h | IFG2 | SFR interrupt flag 2 | Read/write | 0Ah with PUC | Section 16.5.9 |
D0h | UCA1CTL0 | USCI_A1 control 0 | Read/write | 00h with PUC | Section 16.5.1 |
D1h | UCA1CTL1 | USCI_A1 control 1 | Read/write | 01h with PUC | Section 16.5.1 |
D2h | UCA1BR0 | USCI_A1 baud-rate control 0 | Read/write | 00h with PUC | Section 16.5.3 |
D3h | UCA1BR1 | USCI_A1 baud-rate control 1 | Read/write | 00h with PUC | Section 16.5.4 |
D5h | UCA1STAT | USCI_A1 status | Read/write | 00h with PUC | Section 16.5.5 |
D6h | UCA1RXBUF | USCI_A1 receive buffer | Read | 00h with PUC | Section 16.5.6 |
D7h | UCA1TXBUF | USCI_A1 transmit buffer | Read/write | 00h with PUC | Section 16.5.7 |
D8h | UCB1CTL0 | USCI_B1 control 0 | Read/write | 01h with PUC | Section 16.5.1 |
D9h | UCB1CTL1 | USCI_B1 control 1 | Read/write | 01h with PUC | Section 16.5.1 |
DAh | UCB1BR0 | USCI_B1 bit-rate control 0 | Read/write | 00h with PUC | Section 16.5.3 |
DBh | UCB1BR1 | USCI_B1 bit-rate control 1 | Read/write | 00h with PUC | Section 16.5.4 |
DDh | UCB1STAT | USCI_B1 status | Read/write | 00h with PUC | Section 16.5.5 |
DEh | UCB1RXBUF | USCI_B1 receive buffer | Read | 00h with PUC | Section 16.5.6 |
DFh | UCB1TXBUF | USCI_B1 transmit buffer | Read/write | 00h with PUC | Section 16.5.7 |
6h | UC1IE | USCI_A1/B1 interrupt enable | Read/write | 00h with PUC | Section 16.5.10 |
7h | UC1IFG | USCI_A1/B1 interrupt flag | Read/write | 0Ah with PUC | Section 16.5.11 |
Modifying SFR bits
To avoid modifying control bits of other modules, TI recommends setting or clearing the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
USCI_Ax Control 0 Register, USCI_Bx Control 0 Register
UCAxCTL0 and UCBxCTL0 are shown in Figure 16-5 and described in Table 16-3.
Return to Table 16-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCCKPH | UCCKPL | UCMSB | UC7BIT | UCMST | UCMODEx | UCSYNC | |
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | UCCKPH | R/W | 0h | Clock phase select 0b = Data is changed on the first UCLK edge and captured on the following edge. 1b = Data is captured on the first UCLK edge and changed on the following edge. |
6 | UCCKPL | R/W | 0h | Clock polarity select 0b = The inactive state is low. 1b = The inactive state is high. |
5 | UCMSB | R/W | 0h | MSB first select. Controls the direction of the receive and transmit shift register. 0b = LSB first 1b = MSB first |
4 | UC7BIT | R/W | 0h | Character length. Selects 7-bit or 8-bit character length. 0b = 8-bit data 1b = 7-bit data |
3 | UCMST | R/W | 0h | Master mode select 0b = Slave mode 01b = Master mode |
2-1 | UCMODEx | R/W | 0h | USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00b = 3-pin SPI 01b = 4-pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1 10b = 4-pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0 11b = I2C mode |
0 | UCSYNC | R/W | 0h | Synchronous mode enable. Must be 1 for SPI mode. 0b = Asynchronous mode 1b = Synchronous mode |
USCI_Ax Control 1 Register, USCI_Bx Control 1 Register
UCAxCTL1 and UCBxCTL1 are shown in Figure 16-6 and described in Table 16-4.
Return to Table 16-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCSSELx | Reserved | UCSWRST | |||||
rw-0 | rw-0 | rw-0 #SLAU144SPI5426 r0 #SLAU144SPI4984 | rw-0 | rw-0 | rw-0 | rw-0 | rw-1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | UCSSELx | R/W | 0h | USCI clock source select. These bits select the BRCLK source clock in master mode. UCxCLK is always used in slave mode. 00b = Reserved 01b = ACLK 10b = SMCLK 11b = SMCLK |
5-1 | Reserved | R/W | 0h | |
0 | UCSWRST | R/W | 1h | Software reset enable 0b = Disabled. USCI reset released for operation. 1b = Enabled. USCI logic held in reset state. |
USCI_Ax Bit-Rate Control 0 Register, USCI_Bx Bit-Rate Control 0 Register
UCAxBRx and UCBxBRx are shown in Figure 16-7 and described in Table 16-5.
Return to Table 16-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCBRx (low byte) | |||||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UCBRx | R/W | 0h | Bit clock prescaler setting. The 16-bit value of (UCxxBR0 + UCxxBR1 × 256) forms the prescaler value. |
USCI_Ax Bit-Rate Control 1 Register, USCI_Bx Bit-Rate Control 1 Register
UCAxBRx and UCBxBRx are shown in Figure 16-8 and described in Table 16-6.
Return to Table 16-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCBRx (high byte) | |||||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UCBRx | R/W | 0h | Bit clock prescaler setting. The 16-bit value of (UCxxBR0 + UCxxBR1 × 256) forms the prescaler value. |
USCI_Ax Status Register, USCI_Bx Status Register
UCAxSTAT and UCBxSTAT are shown in Figure 16-9 and described in Table 16-7.
Return to Table 16-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCLISTEN | UCFE | UCOE | Reserved | UCBUSY | |||
rw-0 | rw-0 | rw-0 | rw-0 #SLAU144SPI2167 r0 #SLAU144SPI1873 | rw-0 | rw-0 | rw-0 | r-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | UCLISTEN | R/W | 0h | Listen enable. The UCLISTEN bit selects loopback mode. 0b = Disabled 1b = Enabled. The transmitter output is internally fed back to the receiver. |
6 | UCFE | R/W | 0h | Framing error flag. This bit indicates a bus conflict in 4-wire master mode. UCFE is not used in 3-wire master or any slave mode. 0b = No error 1b = Bus error occured |
5 | UCOE | R/W | 0h | Overrun error flag. This bit is set when a character is transferred into UCxRXBUF before the previous character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by software. Otherwise, it will not function correctly. 0b = No error 1b = Overrun error occured |
4-1 | Reserved | R/W | 0h | |
0 | UCBUSY | R | 0h | USCI busy. This bit indicates if a transmit or receive operation is in progress. 0b = USCI inactive 1b = USCI transmitting or receiving |
USCI_Ax Receive Buffer Register, USCI_Bx Receive Buffer Register
UCAxRXBUF and UCBxRXBUF are shown in Figure 16-10 and described in Table 16-8.
Return to Table 16-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCRXBUFx | |||||||
r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | r-0 | r-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UCRXBUFx | R | 0h | The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UCxRXBUF resets the receive-error bits, and UCxRXIFG. In 7-bit data mode, UCxRXBUF is LSB justified and the MSB is always reset. |
USCI_Ax Transmit Buffer Register, USCI_Bx Transmit Buffer Register
UCAxTXBUF and UCBxTXBUF are shown in Figure 16-11 and described in Table 16-9.
Return to Table 16-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCTXBUFx | |||||||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | UCTXBUFx | R/W | 0h | The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted. Writing to the transmit data buffer clears UCxTXIFG. The MSB of UCxTXBUF is not used for 7-bit data and is reset. |
SFR Interrupt Enable 2 Register
IE2 is shown in Figure 16-12 and described in Table 16-10.
Return to Table 16-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCB0TXIE | UCB0RXIE | UCA0TXIE | UCA0RXIE | ||||
rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | These bits may be used by other modules (see the device-specific data sheet). | |||
3 | UCB0TXIE | R/W | 0h | USCI_B0 transmit interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
2 | UCB0RXIE | R/W | 0h | USCI_B0 receive interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
1 | UCA0TXIE | R/W | 0h | USCI_A0 transmit interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
0 | UCA0RXIE | R/W | 0h | USCI_A0 receive interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
SFR Interrupt Flag 2 Register
IFG2 is shown in Figure 16-13 and described in Table 16-11.
Return to Table 16-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCB0TXIFG | UCB0RXIFG | UCA0TXIFG | UCA0RXIFG | ||||
rw-1 | rw-0 | rw-1 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | These bits may be used by other modules (see the device-specific data sheet). | |||
3 | UCB0TXIFG | R/W | 0h | USCI_B0 transmit interrupt flag. UCB0TXIFG is set when UCB0TXBUF is empty. 0b = No interrupt pending 1b = Interrupt pending |
2 | UCB0RXIFG | R/W | 1h | USCI_B0 receive interrupt flag. UCB0RXIFG is set when UCB0RXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending |
1 | UCA0TXIFG | R/W | 0h | USCI_A0 transmit interrupt flag. UCA0TXIFG is set when UCA0TXBUF is empty. 0b = No interrupt pending 1b = Interrupt pending |
0 | UCA0RXIFG | R/W | 1h | USCI_A0 receive interrupt flag. UCA0RXIFG is set when UCA0RXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending |
USCI_A1/B1 Interrupt Enable Register
UC1IE is shown in Figure 16-14 and described in Table 16-12.
Return to Table 16-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Unused | UCB1TXIE | UCB1RXIE | UCA1TXIE | UCA1RXIE | |||
rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | Unused | R/W | 0h | |
3 | UCB1TXIE | R/W | 0h | USCI_B1 transmit interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
2 | UCB1RXIE | R/W | 0h | USCI_B1 receive interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
1 | UCA1TXIE | R/W | 0h | USCI_A1 transmit interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
0 | UCA1RXIE | R/W | 0h | USCI_A1 receive interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled |
USCI_A1/B1 Interrupt Flag Register
UC1IFG is shown in Figure 16-15 and described in Table 16-13.
Return to Table 16-2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Unused | UCB1TXIFG | UCB1RXIFG | UCA1TXIFG | UCA1RXIFG | |||
rw-0 | rw-0 | rw-0 | rw-0 | rw-1 | rw-0 | rw-1 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | Unused | R/W | 0h | |
3 | UCB1TXIFG | R/W | 1h | USCI_B1 transmit interrupt flag. UCB1TXIFG is set when UCB1TXBUF is empty. 0b = No interrupt pending 1b = Interrupt pending |
2 | UCB1RXIFG | R/W | 0h | USCI_B1 receive interrupt flag. UCB1RXIFG is set when UCB1RXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending |
1 | UCA1TXIFG | R/W | 1h | USCI_A1 transmit interrupt flag. UCA1TXIFG is set when UCA1TXBUF empty. 0b = No interrupt pending 1b = Interrupt pending |
0 | UCA1RXIFG | R/W | 0h | USCI_A1 receive interrupt flag. UCA1RXIFG is set when UCA1RXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending |