SLAU144K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
Table 10-1 lists the memory-mapped registers for the Watchdog Timer+.
Address | Acronym | Register Name | Type | Reset | Section |
---|---|---|---|---|---|
120h | WDTCTL | Watchdog timer+ control | Read/write | 6900h with PUC | Section 10.4.1 |
0h | IE1 | SFR interrupt enable 1 | Read/write | 00h with PUC | Section 10.4.2 |
2h | IFG1 | SFR interrupt flag 1 | Read/write | 00h with PUC | Section 10.4.3 |
Watchdog Timer+ Control Register
WDTCTL is shown in Figure 10-2 and described in Table 10-2.
Return to Table 10-1.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WDTPW | |||||||
rw-0 | rw-1 | rw-1 | rw-0 | rw-1 | rw-0 | rw-0 | rw-1 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDTHOLD | WDTNMIES | WDTNMI | WDTTMSEL | WDTCNTCL | WDTSSEL | WDTISx | |
rw-0 | rw-0 | rw-0 | rw-0 | r0(w) | rw-0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | WDTPW | R/W | 69h | Watchdog timer+ password. Always reads as 069h. Must be written as 05Ah. Writing any other value generates a PUC. |
7 | WDTHOLD | R/W | 0h | Watchdog timer+ hold. This bit stops the watchdog timer+. Setting WDTHOLD = 1 when the WDT+ is not in use conserves power. 0b = Watchdog timer+ is not stopped 1b = Watchdog timer+ is stopped |
6 | WDTNMIES | R/W | 0h | Watchdog timer+ NMI edge select. This bit selects the interrupt edge for the NMI interrupt when WDTNMI = 1. Modifying this bit can trigger an NMI. Modify this bit when WDTIE = 0 to avoid triggering an accidental NMI. 0b = NMI on rising edge 1b = NMI on falling edge |
5 | WDTNMI | R/W | 0h | Watchdog timer+ NMI select. This bit selects the function for the RST/NMI pin. 0b = Reset function 1b = NMI function |
4 | WDTTMSEL | R/W | 0h | Watchdog timer+ mode select 0b = Watchdog mode 1b = Interval timer mode |
3 | WDTCNTCL | R/W | 0h | Watchdog timer+ counter clear. Setting WDTCNTCL = 1 clears the count value to 0000h. WDTCNTCL is automatically reset. 0b = No action 1b = WDTCNT = 0000h |
2 | WDTSSEL | R/W | 0h | Watchdog timer+ clock source select 0b = SMCLK 1b = ACLK |
1-0 | WDTISx | R/W | 0h | Watchdog timer+ interval select. These bits select the watchdog timer+ interval to set the WDTIFG flag or generate a PUC. 00b = Watchdog clock source /32768 01b = Watchdog clock source /8192 10b = Watchdog clock source /512 11b = Watchdog clock source /64 |
Interrupt Enable 1 Register
IE1 is shown in Figure 10-3 and described in Table 10-3.
Return to Table 10-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMIIE | WDTIE | ||||||
rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | These bits may be used by other modules. See device-specific data sheet. | |||
4 | NMIIE | R/W | 0h | NMI interrupt enable. This bit enables the NMI interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0b = Interrupt not enabled 1b = Interrupt enabled |
3-1 | These bits may be used by other modules. See device-specific data sheet. | |||
0 | WDTIE | R/W | 0h | Watchdog timer+ interrupt enable. This bit enables the WDTIFG interrupt for interval timer mode. It is not necessary to set this bit for watchdog mode. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0b = Interrupt not enabled 1b = Interrupt enabled |
Interrupt Flag 1 Register
IFG1 is shown in Figure 10-4 and described in Table 10-4.
Return to Table 10-1.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMIIFG | WDTIFG | ||||||
rw-0 | rw-(0) |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | These bits may be used by other modules. See device-specific data sheet. | |||
4 | NMIIFG | R/W | 0h | NMI interrupt flag. NMIIFG must be reset by software. Because other bits in IFG1 may be used for other modules, it is recommended to clear NMIIFG by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0b = No interrupt pending 1b = Interrupt pending |
3-1 | These bits may be used by other modules. See device-specific data sheet. | |||
0 | WDTIFG | R/W | 0h | Watchdog timer+ interrupt flag. In watchdog mode, WDTIFG remains set until reset by software. In interval mode, WDTIFG is reset automatically by servicing the interrupt, or can be reset by software. Because other bits in IFG1 may be used for other modules, it is recommended to clear WDTIFG by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0b = No interrupt pending 1b = Interrupt pending |