SLAU900 November   2023

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Hardware Setup
      1. 2.1.1 Electrostatic Discharge Caution
      2. 2.1.2 Power Configurations and Jumper Settings
      3. 2.1.3 Connecting the Hardware
    2. 2.2 Hardware Description
      1. 2.2.1 Signal Definitions
      2. 2.2.2 Optional Circuitry
  9. 3Software
    1. 3.1 Software Setup
      1. 3.1.1 Operating Systems
      2. 3.1.2 Software Installation
    2. 3.2 Software Description
      1. 3.2.1 Starting the Software
      2. 3.2.2 Software Features
        1. 3.2.2.1 High Level Configuration Page
          1. 3.2.2.1.1 Basic DAC Subpage
        2. 3.2.2.2 Low Level Configuration Page
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1.     Trademarks

2.1.2 Power Configurations and Jumper Settings

The AFE532A3WEVM provides electrical connections to the device supply pins. Table 3-1 and Figure 3-1 shows the power supply connections.

Table 2-1 AFE532A3WEVM Power Supply Inputs
AFE532A3WEVM Connector Supply Name Voltage Range
J15 VDD 3 V to 5.5 V; remove jumper J18 if applying an external VDD to the device.
J16 GND 0 V
J17 VSS –1.5 V to –5 V; required to use the inverting op-amp circuit.
J8 PVDD PVDD supply for the VOUT1 current boost circuit
GUID-20230726-SS0I-D2PH-MZSN-QGS26FLLJ8ZH-low.svg Figure 2-1 AFE532A3WEVM Power Supply Inputs
Table 3-2 provides the details of the configurable jumper settings on the AFE532A3WEVM.
Table 2-2 AFE532A3WEVM Jumper Settings
Jumper Default Position Available Option Description
J1 Open: VOUT1 disconnected from GPIO/SDO Closed: VOUT1 connected to GPIO/SDO Connects VOUT1 to GPIO/SDO
J2 Open: IOUT disconnected from FB1 Closed: IOUT connected to FB1 Connects IOUT to FB1 (comparator input)
J3 Open: VOUT0 disconnected from op-amp input Closed: VOUT0 connected to op-amp input Connects VOUT0 to the op-amp input pin
J4

Open: IOUT disconnected from AIN1

 Closed: IOUT connected to AIN1 Connects IOUT to AIN1 (ADC input)
J5 Open: FB1 disconnected from 10-kΩ pullup resistor Closed: FB1 connected to 10-kΩ pullup resistor Connect FB1 to a 10-kΩ pullup resistor
J6 Open: IOUT disconnected from 4.99-Ω load Closed: IOUT connected to 4.99-Ω load Connects IOUT to a 4.99-Ω load
J7 Closed: VOUT1 connected to FB1 Open: VOUT1 disconnected to FB1 Connects VOUT1 to FB1
J9 Open: IOUT disconnected from IOUT2 Closed: IOUT connected to IOUT2 Connects IOUT to IOUT2
J10 Open: IOUT2 disconnected from 4.99-Ω load Closed: IOUT2 connected to 4.99-Ω load Connects IOUT2 to a 4.99-Ω load
J12 Closed: FTDI SPI and I2C enabled Open: FTDI SPI and I2C disabled Enables the FTDI SPI and I2C level translators
J14 Closed: FTDI GPIOs enabled Open: FTDI GPIOs disabled Enables the FTDI GPIO level translators
J18 Closed: 3.3-V supply connected to VDD Open: 3.3-V supply disconnected from VDD AFE VDD supply selection
J20 1-2: GPIO connected to AFE 2-3: SDO connected to AFE I2C or SPI selection
J23 1-2: SCL connected to AFE 2-3: SYNC connected to AFE I2C or SPI selection
J25 1-2: A0 connected to AFE 2-3: SDI connected to AFE I2C or SPI selection
J29 1-2: SDA connected to AFE 2-3: SCLK connected to AFE I2C or SPI selection

If an external supply is applied to J15, then remove jumper J18 to disconnect the 3.3-V regulator supply from the AFEx32A3W VDD pin.

GPIO2 and GPIO3 from the onboard controller are configured as outputs when the AFE532A3WEVM is controlled with the GUI. GPIO2 from the onboard controller is connected to the GPIO/SDO pin of the AFEx32A3W. If the AFE SDO pin is configured as an output, then remove jumper J14 to disable the GPIOs from the onboard controller.

Figure 3-2 shows the default jumper settings on the AFE532A3WEVM.

GUID-20230830-SS0I-G2Z8-WV87-H1XJN0WWKKMC-low.svg Figure 2-2 AFE532A3WEVM Default Jumper Settings

The AFE532A3WEVM has an optional inverting op-amp circuit that can be used to invert the VOUT0 output of the primary AFEx32A3W. Figure 3-3 shows how to configure the jumpers to enable the inverting op-amp circuit. VSS is connected to the negative supply of the inverting op-amp. Connect a –1.5-V to –5-V supply to J17 before closing jumper J3. The positive supply of the inverting op-amp is connected to ground.

GUID-20230830-SS0I-MWVF-CN9W-DQX8V2GD80PK-low.svg Figure 2-3 AFE532A3WEVM Inverting Op-amp Jumper Settings

The IOUTs of the primary and auxiliary AFEx32A3W devices can be connected in parallel to increase the total current output. Figure 3-4 shows the jumper configuration to connect the IOUTs in parallel. Close jumper J6 and/or jumper J10 to connect the resistive load to the parallel IOUT. An external VDD needs to be used if the combined current output exceeds the current limit of the USB port and/or the 500-mA current rating of the onboard regulator.

GUID-20230830-SS0I-XVPZ-KQ5G-W9TKLBZ3HMVX-low.svg Figure 2-4 AFE532A3WEVM Parallel IOUT Jumper Settings

The AFEx32A3W can be used to monitor signals using the integrated programmable comparator. Figure 3-5 shows how to configure the AFE532A3WEVM jumpers to connect the IOUT pin to the comparator input and connect the comparator output to the GPIO/SDO pin. When the voltage across the 4.99-Ω load crosses a programmed threshold, the comparator output connected to the GPIO/SDO pin can be used to trigger alarm conditions or enter power-down mode.

GUID-20230830-SS0I-RH5B-N1D1-CBNM82C4SSPS-low.svg Figure 2-5 AFE532A3WEVM Comparator Input Jumper Settings

Figure 3-6 shows the jumper configuration to connect the IOUT pin to the ADC input. The ADC can be used to monitor the IOUT when the IOUT is connected to the 4.99-Ω load.

GUID-20230830-SS0I-DTR3-DBN6-NJ9K4CZKCPTG-low.svg Figure 2-6 AFE532A3WEVM ADC Input Jumper Settings