SLAU900 November   2023

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Hardware Setup
      1. 2.1.1 Electrostatic Discharge Caution
      2. 2.1.2 Power Configurations and Jumper Settings
      3. 2.1.3 Connecting the Hardware
    2. 2.2 Hardware Description
      1. 2.2.1 Signal Definitions
      2. 2.2.2 Optional Circuitry
  9. 3Software
    1. 3.1 Software Setup
      1. 3.1.1 Operating Systems
      2. 3.1.2 Software Installation
    2. 3.2 Software Description
      1. 3.2.1 Starting the Software
      2. 3.2.2 Software Features
        1. 3.2.2.1 High Level Configuration Page
          1. 3.2.2.1.1 Basic DAC Subpage
        2. 3.2.2.2 Low Level Configuration Page
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1.     Trademarks

2.2.2 Optional Circuitry

The AFE532A3WEVM has optional circuitry that can be used to evaluate the AFEx32A3W.

The AFEx32A3W can be used in optical module applications that require up to a 300 mA current source and a negative bias voltage. The negative bias voltage is generated by connecting the voltage output of the AFEx32A3W to an inverting op-amp. Figure 3-7 shows the block diagram for the negative bias circuit.

GUID-20230830-SS0I-ZF6V-Z2RW-XLNQZCJLRTBJ-low.svgFigure 2-7 AFE532A3WEVM Negative Bias Circuit Block Diagram

Figure 3-8 shows the 2.8-mm × 3.6-mm negative bias circuit layout. The layout consists of the AFEx32A3W, OPA310, two size-0201 resistors, and three size-0201 capacitors.

GUID-20230830-SS0I-P9JX-1BG4-N5TQ4ZF8GK39-low.svgFigure 2-8 AFE532A3WEVM Negative Bias Circuit Layout

The output current capability of the AFEx32A3W VOUT channels can be increased with an external current boost circuit. Figure 3-7 shows the block diagram for the high current, voltage output circuit. Q1 is not populated on the AFE532A3WEVM. Remove the shunt from J7 before populating Q1. Connect PVDD to pin 1 of J8 and connect the load to the AFEx32A3W FB1 pin on pin 6 of J24.

GUID-20230830-SS0I-5QLH-LD1T-H7JQ7XK53NSF-low.svg Figure 2-9 AFE532A3WEVM High Current Output Stage Block Diagram