SLVAF95 april   2023 TPS7H5001-SP

 

  1.   Abstract
  2.   Trademarks
  3.   Description
  4.   Features
  5.   Applications
  6. 1System Overview
    1. 1.1 Block Diagram
    2. 1.2 Design Considerations
    3. 1.3 System Design Theory
      1. 1.3.1 Switching Frequency
      2. 1.3.2 Transformer
      3. 1.3.3 RCD and Diode Clamp
      4. 1.3.4 Output Diode and MOSFET
      5. 1.3.5 Output Filter and Capacitance
      6. 1.3.6 Compensation
      7. 1.3.7 Controller Passives
  7. 2Test Results
    1. 2.1 Testing and Results
      1. 2.1.1 Test Setup
      2. 2.1.2 Test Results
        1. 2.1.2.1 Efficiency
        2. 2.1.2.2 Frequency Response
        3. 2.1.2.3 Thermal Characteristics
        4. 2.1.2.4 Output Voltage Ripple
        5. 2.1.2.5 Load Step
        6. 2.1.2.6 Start-Up
        7. 2.1.2.7 Shutdown
        8. 2.1.2.8 Component Stresses
  8. 3Design Files
    1. 3.1 Schematics
    2. 3.2 Bill of Materials
    3. 3.3 Assembly Drawings
  9. 4Related Documentation

1.2 Design Considerations

The TPS7H5001-SP flyback board uses the TPS7H5001-SP and UCC5304 devices to create a synchronous buck converter to bring the 28-V battery voltage rail into a 5-V rail at 10 A for intermediate rails of space-grade power systems. The limiter of the output current in the design is the bottom-side GaN FET heat. Due to the roughly 150-mA peak current capability of the primary switching outputs of the TPS7H5001, the UCC5304 gate driver is used to amplify the current to provide the FETs of the synchronous buck with sufficient drive. These outputs are not dependent on the TPS7H5001-SP, and can be increased or decreased depending on the design. While isolated converters typically have isolated feedback incorporated into designs, this design capability is not focused on so the design of the other passives in the converter can be explained. Throughout the design process of the converter, equations were used to determine the starting values. Sometimes the value in an equation in this section does not exactly match what is shown in the schematic. Most of the time, this is due to rounding caused by values available in the lab.