SLVUCQ6 july   2023 TPS7H2211-SEP

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Alternate Board Configurations
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 EVM Connectors and Test Points
  7. 3Implementation Results
    1. 3.1 Default Configuration Results
    2. 3.2 Parallel Configuration Results
  8. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Board Layout
    3. 4.3 Bill of Materials (BOM)
  9. 5Related Documentation

Alternate Board Configurations

If a custom configuration is desired, then users need to refer to the TPS7H2211 data sheet to calculate the values of the passive components around the device and note any operational requirements.

In addition to the default EVM configuration, this user's guide provides an example for how the TPS7H2211EVM can be configured for parallel operation. The enable (EN) and overvoltage protection (OVP) specifications for the parallel configuration are the same as what is used for the default configuration. However, this configuration is capable of providing up to double the output current compared to the default configuration.

Table 1-2 TPS7H2211EVM Parallel Configuration
SpecificationValueDescription
Input Voltage

VIN

13 VFalls within the recommended device input voltage range of 4.5 to 14 V.
Output Current

IOUT

0 to 7 ADoes not exceed maximum device continuous current of 3.5 A per device.
EN Turn-on Voltage

VINEN_RISE

7.4 V

Typical EN turn-on and turn-off values.

Set by:

R3 (RTOP_EN) = 100 kΩ

R4 (RBOT_EN) = 9.31 kΩ

R15 populated

EN Turn-off Voltage

VINEN_FALL

6.1 V
OVP Enter Voltage

VINOVP_RISE

13.5 V

Typical OVP enter and exit values.

Set by:

R2 (RTOP_OVP) = 100 kΩ

R5 (RBOT_OVP) = 9.31 kΩ

R17 populated

OVP Exit Voltage

VINOVP_FALL

13.4 V
Soft Start Time

tSS

approx. 10.9 ms

Typical time to go from 10% to 90% of the final voltage.

Set by:

C13 (CSS) = 68 nF

C28 (CSS) = 68 nF

R16 populated

More detailed information about the parallel EVM configuration can be found in Figure 5-2 and Table 5-2.