SNLA443 December 2023 DP83869HM
Verify the frequency and signal integrity. For link integrity the clock must be 25 MHz ±50 ppm. If using a crystal as the clock source, probe the CLK_OUT signal. Probing the crystal can change the capacitive loading therefore changing the operational frequency. The default signal on CLK_OUT is a buffered version of the XI reference and provides a representative measurement.