SPRUIS4E March   2022  – January 2024

 

  1.   1
  2.   Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Key Features
    2. 1.2 Thermal Compliance
    3. 1.3 REACH Compliance
    4. 1.4 EMC, EMI, and ESD Compliance
  5. 2J721E EVM Overview
    1. 2.1 J721E EVM Board Identification
    2. 2.2 J721E SOM Component Identification
    3. 2.3 Jacinto7 Common Processor Components Identification
    4. 2.4 Quad Ethernet Components Identification
  6. 3EVM User Setup/Configuration
    1. 3.1 Power Requirements
    2. 3.2 Power ON Switch and Power LEDs
      1. 3.2.1 Over Voltage and Under Voltage Protection Circuit
      2. 3.2.2 Power Regulators and Power Status LEDs
    3. 3.3 EVM Reset/Interrupt Push Buttons
    4. 3.4 EVM DIP Switches
      1. 3.4.1 EVM Configuration DIP Switch
      2. 3.4.2 SOM Configuration DIP Switch
      3. 3.4.3 Boot Modes
      4. 3.4.4 Other Selection Switches
    5. 3.5 EVM UART/COM Port Mapping
    6. 3.6 JTAG Emulation
  7. 4J721E EVM Hardware Architecture
    1. 4.1  J721E EVM Hardware Top level Diagram
    2. 4.2  J721E EVM Interface Mapping
    3. 4.3  I2C Address Mapping
    4. 4.4  GPIO Mapping
    5. 4.5  Power Supply
      1. 4.5.1 Power Sequencing
      2. 4.5.2 Voltage Supervisor
      3. 4.5.3 DDR I/O Voltage Selection
        1. 4.5.3.1 J721E SoC S2R Logic Flow Diagram
        2. 4.5.3.2 J721E SoC MCU Only Operation
        3. 4.5.3.3 Power Monitoring
    6. 4.6  Reset
    7. 4.7  Clock
      1. 4.7.1 Processor’s Primary Clock
      2. 4.7.2 Processor’s Secondary/SERDES Ref Clock
      3. 4.7.3 EVM Peripheral Ref Clock
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 OSPI Interface
      3. 4.8.3 UFS Interface
      4. 4.8.4 MMC Interface
        1. 4.8.4.1 MMC0 - eMMC Interface
        2. 4.8.4.2 MMC1 – Micro SD Interface
      5. 4.8.5 Board ID EEPROM Interface
      6. 4.8.6 Boot EEPROM Interface
    9. 4.9  MCU Ethernet Interface
      1. 4.9.1 Gigabit Ethernet PHY Default Configuration
    10. 4.10 QSGMII Ethernet Interface
    11. 4.11 PCIe Interface
      1. 4.11.1 X1 Lane PCIe Interface
      2. 4.11.2 X2 Lane PCIe Interface
      3. 4.11.3 M.2 PCIe Interface
    12. 4.12 USB Interface
      1. 4.12.1 USB 3.1 Interface
      2. 4.12.2 USB 2.0 Interface
      3. 4.12.3 USB 3.0 Micro AB Interface (Reserved Port)
    13. 4.13 CAN Interface
    14. 4.14 FPD Interface (Audio Deserializer)
    15. 4.15 FPD Panel Interface (DSI Video Serializer)
    16. 4.16 Display Serial Interface (DSI) FPC
    17. 4.17 Audio Interface
    18. 4.18 Display Port Interface
    19. 4.19 MLB Interface
    20. 4.20 I3C Interface
    21. 4.21 ADC Interface
    22. 4.22 RTC Interface
    23. 4.23 Apple Authentication Header
    24. 4.24 EVM Expansion Connectors
    25. 4.25 ENET Expansion Connector
      1. 4.25.1 Power Requirements
      2. 4.25.2 Clock
        1. 4.25.2.1 Main Clock
        2. 4.25.2.2 Optional Clock
      3. 4.25.3 Reset Signals
      4. 4.25.4 Ethernet Interface
        1. 4.25.4.1 Quad Port SGMII PHY Default Configuration
      5. 4.25.5 Board ID EEPROM Interface
    26. 4.26 CSI Expansion Connector
  8. 5Revision History

4.12.2 USB 2.0 Interface

The USB1 port of J721E SoC is used for USB 2.0 interface in J721E EVM. The USB1 signals are connected to upstream port of USB 2.0 Hub (TUSB4041IPAPR). The four downstream ports from USB Hub are connected are shown below:

  • 2 USB ports are terminated to Type A Stacked Connector (AU-Y1008-2)
  • 1 USB port is connected to 4 Pin Header (PCIe Card - WiFi/BT)
  • 1 USB port is connected to EVM Expansion connector

The reference clock to the USB HUB is provided using 24 MHz crystal and also an optional clock input from the Peripheral clock generator using a resistor mux. The default clock source is set to crystal.

GUID-C22C4DB8-BE89-48DC-A566-F0EEFE163474-low.gif Figure 4-28 USB Hub Reference Clock Circuit

Figure 4-29 shows the USB HUB strapping options.

GUID-B57C51DA-91A6-48C6-A308-B4B156C0F36D-low.gif Figure 4-29 USB Hub Settings Circuit

And the USB ID pin is pulled low to operate the SoC in Host mode.

GUID-E8615945-9E89-4A43-8C80-07005F8C7E3B-low.gif Figure 4-30 USB1 ID Setting for HUB

To PCIe Card Wi-Fi/BT:

The downstream port1 of USB HUB is connected to the Wi-Fi/BT header (J2) on the CP board. The power to the WiFi header is provided through current limit load switch with integrated ESD protection device TPD3S014DBVR. The power is controlled by USB hub power enable signal USB1_DN1_PE.

To Stacked Connector:

The downstreams port2 and 3 of USB HUB is connected to the stacked USB 2.0 Type-A receptacle AU-Y1008-2 on the CP board. The power to the USB Type-A receptacle is provided through current limit load switch with integrated ESD protection device TPD3S014DBVR for each port. The power is controlled by USB hub power enable signals USB1_DN2_PE and USB1_DN3_PE.

To Expansion Connector:

The downstream port4 of USB HUB is connected to EVM Expansion connector. The current version of EVM is not supporting any peripherals on this port. It is reserved for future development.