SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-1757 lists the memory-mapped registers for the MCU_CPSW0_ALE. All register offset addresses not listed in Table 12-1757 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4600 0000h |
Offset | Acronym | Register Name | MCU_CPSW0_NUSS_ALE Physical Address |
---|---|---|---|
0003E000h | CPSW_ALE_MOD_VER | ALE Module and Version Register | 4603 E000h |
0003E004h | CPSW_ALE_STATUS | ALE Status Register | 4603 E004h |
0003E008h | CPSW_ALE_CONTROL | ALE Control Register | 4603 E008h |
0003E00Ch | CPSW_ALE_CTRL2 | ALE Control 2 Register | 4603 E00Ch |
0003E010h | CPSW_ALE_PRESCALE | ALE Prescale Register | 4603 E010h |
0003E014h | CPSW_ALE_AGING_CTRL | ALE Aging Control Register | 4603 E014h |
0003E01Ch | CPSW_ALE_NXT_HDR | ALE Next Header Register | 4603 E01Ch |
0003E020h | CPSW_ALE_TBLCTL | ALE Table Control Register | 4603 E020h |
0003E034h | CPSW_ALE_TBLW2 | ALE LUT Table Word 2 Register | 4603 E034h |
0003E038h | CPSW_ALE_TBLW1 | ALE LUT Table Word 1 Register | 4603 E038h |
0003E03Ch | CPSW_ALE_TBLW0 | ALE LUT Table Word 0 Register | 4603 E03Ch |
0003E040h + formula | CPSW_Iy_ALE_PORTCTL0_y | ALE Port Control 0 to 1 Registers | 4603 E040h + formula |
0003E090h | CPSW_ALE_UVLAN_MEMBER | ALE Unknown VLAN Member Mask Register | 4603 E090h |
0003E094h | CPSW_ALE_UVLAN_URCAST | ALE Unknown VLAN Unregistered Multicast Flood Mask Register | 4603 E094h |
0003E098h | CPSW_ALE_UVLAN_RMCAST | ALE Unknown VLAN Registered Multicast Flood Mask Register | 4603 E098h |
0003E09Ch | CPSW_ALE_UVLAN_UNTAG | ALE Unknown VLAN force Untagged Egress Mask Register | 4603 E09Ch |
0003E0B8h | CPSW_ALE_STAT_DIAG | ALE Statistic Output Diagnostic Register | 4603 E0B8h |
0003E0BCh | CPSW_ALE_OAM_LB_CTRL | ALE OAM Loopback Control Register | 4603 E0BCh |
0003E0C0h | CPSW_ALE_MSK_MUX0 | ALE Mask Mux 0 Register | 4603 E0C0h |
0003E0C4h + formula | CPSW_Ix_ALE_MSK_MUXx | ALE Mask Mux 1 to 3 Registers | 4603 E0C4h + formula |
0003E0FCh | CPSW_ALE_EGRESSOP | ALE Egress Operation Register | 4603 E0FCh |
0003E100h | CPSW_ALE_POLICECFG0 | ALE Policing Configuration 0 Register | 4603 E100h |
0003E104h | CPSW_ALE_POLICECFG1 | ALE Policing Configuration 1 Register | 4603 E104h |
0003E108h | CPSW_ALE_POLICECFG2 | ALE Policing Configuration 2 Register | 4603 E108h |
0003E10Ch | CPSW_ALE_POLICECFG3 | ALE Policing Configuration 3 Register | 4603 E10Ch |
0003E110h | CPSW_ALE_POLICECFG4 | ALE Policing Configuration 4 Register | 4603 E110h |
0003E118h | CPSW_ALE_POLICECFG6 | ALE Policing Configuration 6 Register | 4603 E118h |
0003E11Ch | CPSW_ALE_POLICECFG7 | ALE Policing Configuration 7 Register | 4603 E11Ch |
0003E120h | CPSW_ALE_POLICETBLCTL | ALE Policing Table Control Register | 4603 E120h |
0003E124h | CPSW_ALE_POLICECONTROL | ALE Policing Control Register | 4603 E124h |
0003E128h | CPSW_ALE_POLICETESTCTL | ALE Policing Test Control Register | 4603 E128h |
0003E12Ch | CPSW_ALE_POLICEHSTAT | ALE Policing Hit Status Register | 4603 E12Ch |
0003E134h | CPSW_ALE_THREADMAPDEF | ALE THREAD Mapping Default Value Register | 4603 E134h |
0003E138h | CPSW_ALE_THREADMAPCTL | ALE THREAD Mapping Control Register | 4603 E138h |
0003E13Ch | CPSW_ALE_THREADMAPVAL | ALE THREAD Mapping Value Register | 4603 E13Ch |
CPSW_ALE_MOD_VER is shown in Figure 12-838 and described in Table 12-1616.
Return to Summary Table.
The Module and Version Register identifies the module identifier of the ALE_2g64i module.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
MODULE_ID | |||||||
R-29h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODULE_ID | |||||||
R-29h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RTL_VERSION | MAJOR_REVISION | ||||||
R-7h | R-1h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CUSTOM_REVISION | MINOR_REVISION | ||||||
R-0h | R-4h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODULE_ID | R | 29h | ALE module ID. |
15-11 | RTL_VERSION | R | 7h | RTL Version. |
10-8 | MAJOR_REVISION | R | 1h | Major Revision. |
7-6 | CUSTOM_REVISION | R | 0h | Custom Revision. |
5-0 | MINOR_REVISION | R | 4h | Minor Revision. |
CPSW_ALE_STATUS is shown in Figure 12-839 and described in Table 12-1618.
Return to Summary Table.
The ALE status provides information on the ALE configuration and state. The RAMDEPTH is used to determine how IPv6 entries are stored in the table. IPv6 entries are stored in two entries where IPv6 Entry Hi is designated by the odd slice index and Lo is designated by the even slice index. The slice index is above the ram depth like {SlixeIndex,RamIndex}. So for a 64 deep RAM index of 0x005, the Hi portion of the IPv6 entry is located at 0x005|0x040 and the Lo portion is located at 0x005&(~0x040).
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
POLCNTDIV8 | |||||||
R-1h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAMDEPTH128 | RAMDEPTH32 | RESERVED | KLUENTRIES | ||||
R-0h | R-1h | R-X | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | |
15-8 | POLCNTDIV8 | R | 1h | This is the number of policer engines the ALE implements divided by 8. A value of 4 indicates 32 policer engines total. |
7 | RAMDEPTH128 | R | 0h | The number of ALE entries per slice of the table when this is set it indicates the depth is 128 if both RAMDEPTH128 and RAMDEPTH32 are zero the depth is 64. |
6 | RAMDEPTH32 | R | 1h | The number of ALE entries per slice of the table when this is set it indicates the depth is 32 if both RAMDEPTH128 and RAMDEPTH32 are zero the depth is 64. |
5 | RESERVED | R | 0h | |
4-0 | KLUENTRIES | R | 0h | This is the number of table entries total divided by 1024. A value of 1h indicates 1024 table entries. A value of 8h indicates 8192 table entries. |
CPSW_ALE_CONTROL is shown in Figure 12-840 and described in Table 12-1620.
Return to Summary Table.
The ALE Control Register is used to set the ALE modes used for all ports.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ENABLE_ALE | CLEAR_TABLE | AGE_OUT_NOW | RESERVED | MIRROR_DP | |||
R/W-0h | R/W-0h | R/W-0h | R/W-X | R/W-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
UPD_BW_CTRL | RESERVED | MIRROR_TOP | |||||
R/W-0h | R/W-X | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
UPD_STATIC | RESERVED | UVLAN_NO_LEARN | MIRROR_MEN | MIRROR_DEN | MIRROR_SEN | RESERVED | EN_HOST_UNI_FLOOD |
R/W-0h | R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-X | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LEARN_NO_VLANID | ENABLE_VID0_MODE | ENABLE_OUI_DENY | ENABLE_BYPASS | BCAST_MCAST_CTL | ALE_VLAN_AWARE | ENABLE_AUTH_MODE | ENABLE_RATE_LIMIT |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ENABLE_ALE | R/W | 0h | Enable ALE. 0h = Drop all packets 1h = Enable ALE packet processing |
30 | CLEAR_TABLE | R/W | 0h | Clear ALE address table. Setting this bit causes the ALE hardware to write all table bit values to zero. Software must perform a clear table operation as part of the ALE setup/configuration process. Setting this bit causes all ALE accesses to be held up for 64 clocks while the clear is performed. Access to all ALE registers will be blocked (wait states) until the 64 clocks have completed. This bit cannot be read as one because the read is blocked until the clear table is completed at which time this bit is cleared to zero. |
29 | AGE_OUT_NOW | R/W | 0h | Age Out Address Table Now. Setting this bit causes the ALE hardware to remove (free up) any ageable table entry that does not have a set touch bit. This bit is cleared when the age out process has completed. This bit may be read. The age out process takes four times the number of table entries clock cycles (4096 cycles for 1K addresses) best case (no ale packet processing during ageout) and sixty five times the number of table entries clock cycles (66560 cycles for 1K addresses) absolute worst case. |
28-25 | RESERVED | R/W | 0h | |
24 | MIRROR_DP | R/W | 0h | Mirror Destination Port. This field defines the port to which destination traffic destined will be duplicated. That is all traffic that is forwarded to this port will also be mirrored to the MIRROR_TOP port. |
23-21 | UPD_BW_CTRL | R/W | 0h | The UPD_BW_CTRL field allows for up to 8 times the rate in which adds, updates, touches, writes, and aging updates can occur. At frequencies of 350Mhz, the table update rate should be at it lowest or 5 Million updates per second. When operating the switch core at frequencies or above, the UPD_BW_CTRL can be programmed more aggressive. If the UPD_BW_CTRL is set but the frequency of the switch subsystem is below the associated value, ALE will drop packets due to insufficient time to complete lookup under high traffic loads. 0h = 350Mhz, 5M 1h = 359Mhz, 11M 2h = 367Mhz, 16M 3h = 375Mhz, 22M 4h = 384Mhz, 28M 5h = 392Mhz, 34M 6h = 400Mhz, 39M 7h = 409Mhz, 45M |
20-17 | RESERVED | R/W | 0h | |
16 | MIRROR_TOP | R/W | 0h | Mirror To Port. This field defines the destination port for the mirror traffic. If the traffic is received or transmitted on the mirror destination port it will not be duplicated. Traffic defined as mirror traffic only may be dropped by the switch due to congestion. |
15 | UPD_STATIC | R/W | 0h | Update Static Entries - A static Entry is an entry that is not agable. When clear this bit will prevent any static entry (agable bit clear) from being updated due to port change. When set it allows static entries (agable bit clear) to update the source port if required. This bit should normally be 0h for most switch configurations. |
14 | RESERVED | R/W | 0h | |
13 | UVLAN_NO_LEARN | R/W | 0h | Unknown VLAN No Learn. This field when set will prevent source addresses of unknown VLAN IDs from being automatically added into the look up table if learning is enabled. |
12 | MIRROR_MEN | R/W | 0h | Mirror Match Entry Enable. This field enables the match mirror option. When this bit is set any traffic whose destination, source, VLAN or OUI matches the ~imirror_midx entry index will have that traffic also sent to the ~imirror_top port. |
11 | MIRROR_DEN | R/W | 0h | Mirror Destination Port Enable - This field enables the destination port mirror option. When this bit is set any traffic destined for the ~imirror_dp port will have its transmit traffic also sent to the ~imirror_top port. |
10 | MIRROR_SEN | R/W | 0h | Mirror Source Port Enable - This field enables the source port mirror option. When this bit is set any port with the Iy_REG_P0_MIRROR_SP set in the CPSW_Iy_ALE_PORTCTL0_y registers set will have its received traffic also sent to the MIRROR_TOP port. |
9 | RESERVED | R/W | X | |
8 | EN_HOST_UNI_FLOOD | R/W | 0h | Unknown unicast packets flood to host. 0h = Unknown unicast packets are not sent to the host. 1h = Unknown unicast packets flood to host port as well as other ports. |
7 | LEARN_NO_VLANID | R/W | 0h | Learn No VID. 0h = VID is learned with the source address. 1h = VID is not learned with the source address (source address is not tied to VID). Determines the entry type. |
6 | ENABLE_VID0_MODE | R/W | 0h | Enable VLAN ID = 0 Mode 0h = Process the priority tagged packet with VID = PORT_VLAN[11:0]. 1h = Process the priority tagged packet with VID = 0h. |
5 | ENABLE_OUI_DENY | R/W | 0h | Enable OUI Deny Mode. 0h = Any packet source address matching an OUI address table entry will be dropped to the host unless the destination address matches with a supervisory destination address table entry. 1h = Any packet with a non-matching OUI source address will be dropped to the host unless the packet destination address matches a supervisory destination address table entry. |
4 | ENABLE_BYPASS | R/W | 0h | ALE Bypass. When set, packets received on non-host ports are sent to the host. It is expected that packets from the host are directed to the particular port. 0h = No bypass 1h = Bypass the ALE |
3 | BCAST_MCAST_CTL | R/W | 0h | Rate Limit Transmit mode. 0h = Broadcast and multicast rate limit counters are received port based. 1h = Broadcast and multicast rate limit counters are transmit port based. |
2 | ALE_VLAN_AWARE | R/W | 0h | ALE VLAN Aware. Determines how traffic is forwarded using VLAN rules. 0h = Simple switch rules, packets forwarded to all ports for unknown destinations. 1h = VLAN Aware rules, packets forwarded based on VLAN members |
1 | ENABLE_AUTH_MODE | R/W | 0h | Enable MAC Authorization Mode. Mac authorization mode requires that all table entries be made by the host software. There is no auto learning of addresses in authorization mode and the packet will be dropped if the source address is not found (and the destination address is not a multicast address with the super table entry bit set). 0h = The ALE is not in MAC authorization mode 1h = The ALE is in MAC authorization mode |
0 | ENABLE_RATE_LIMIT | R/W | 0h | Enable Broadcast and Multicast Rate Limit 0h = Broadcast/Multicast rates not limited 1h = Broadcast/Multicast packet reception limited to the port control register rate limit fields. |
CPSW_ALE_CTRL2 is shown in Figure 12-841 and described in Table 12-1622.
Return to Summary Table.
The ALE Control 2 Register is used to set the extended features used for all ports.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E00Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TRK_EN_DST | TRK_EN_SRC | TRK_EN_PRI | RESERVED | TRK_EN_IVLAN | RESERVED | TRK_EN_SIP | TRK_EN_DIP |
R/W-0h | R/W-0h | R/W-0h | R/W-X | R/W-0h | R/W-X | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DROP_BADLEN | NODROP_SRCMCST | DEFNOFRAG | DEFLMTNXTHDR | RESERVED | TRK_BASE | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-X | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MIRROR_MIDX | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | TRK_EN_DST | R/W | 0h | Trunk Enable Destination Address. This field enables the destination MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. |
30 | TRK_EN_SRC | R/W | 0h | Trunk Enable Source Address. This field enables the source MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. |
29 | TRK_EN_PRI | R/W | 0h | Trunk Enable Priority. This field enables the VLAN Priority bits to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. In the event that DSCP mapping is enabled and there is no VLAN the DSCP priority will be used. For all other non IP frames without VLAN the port default priority is used. |
28 | RESERVED | R/W | 0h | |
27 | TRK_EN_IVLAN | R/W | 0h | Trunk Enable Inner VLAN. This field enables the inner VLAN ID value (C-VLANID) to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. |
26 | RESERVED | R/W | 0h | |
25 | TRK_EN_SIP | R/W | 0h | Trunk Enable Source IP Address. This field enables the source IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag, Priority tagged, VLAN tagged, Q-in-Q double tagging for both IPV6 and IPV4. |
24 | TRK_EN_DIP | R/W | 0h | Trunk Enable Destination IP Address. This field enables the destination IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag, Priority tagged, VLAN tagged, Q-in-Q double tagging for both IPV6 and IPV4. |
23 | DROP_BADLEN | R/W | 0h | Drop Bad Length will drop any packet that the 802.3 length field is larger than the packet. Ethertypes 0-1500 are 802.3 lengths, all others are Ether types. |
22 | NODROP_SRCMCST | R/W | 0h | No Drop Source Multicast will disable the dropping of any source address with the multicast bit set. |
21 | DEFNOFRAG | R/W | 0h | Default No Frag field will cause an IPv4 fragmented packet to be dropped if a VLAN entry is not found. |
20 | DEFLMTNXTHDR | R/W | 0h | Default limit next header field will cause an IPv4 protocol or IPv6 next header packet to be dropped if a VLAN entry is not found and the protocol or next header does not match the CPSW_ALE_NXT_HDR register values. |
19 | RESERVED | R/W | X | |
18-16 | TRK_BASE | R/W | 0h | Trunk Base. This field is the hash formula starting value. Changing this value will cause the packet distribution on trunk ports to be changed. If all the [31]TRK_EN_DST, [30]TRK_EN_SRC, [29]TRK_EN_PRI and [27]TRK_EN_VLAN bits are cleared (value: 0h), this value is used as the distribution index. That is a 0h will select the 1st bit of an 'N' link trunk, a 1h will select the second, etc. Below is the distribution across the trunk links. The first number in the sequence indicates the traffic is sent to the lowest numbered port of a trunk group. For example if you have a 3 port trunk, the hash result 0h will go to the base port (0), hash result 1h will go to the highest port of the trunk group (2), hash result 2h will go to the middle port (1), etc. 1h = 00000000 2h = 01010101 3h = 02102102 4h = 03210321 |
15-6 | RESERVED | R/W | 0h | |
5-0 | MIRROR_MIDX | R/W | 0h | Mirror Index. This field is the ALE lookup table entry index that when a match occurs will cause this traffic to be mirrored to the MIRROR_TOP port. That is any VLAN, ONU or address with or withou VLAN can be selected for traffic mirroring. |
CPSW_ALE_PRESCALE is shown in Figure 12-842 and described in Table 12-1624.
Return to Summary Table.
The ALE Prescale Register is used to set the Broadcast and Multicast rate limiting prescaler value.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ALE_PRESCALE | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19-0 | ALE_PRESCALE | R/W | 0h | ALE Prescale. The input clock is divided by this value for use in the multicast/broadcast rate limiters. The minimum operating value is 10h. The prescaler is off when the value is zero. |
CPSW_ALE_AGING_CTRL is shown in Figure 12-843 and described in Table 12-1626.
Return to Summary Table.
The ALE Aging Control sets the aging interval which will cause periodic aging to occur. This value specifies the minimum time between aging starts.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PRESCALE_2_DISABLE | PRESCALE_1_DISABLE | RESERVED | |||||
R/W-0h | R/W-0h | R/W-X | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ALE_AGING_TIMER | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ALE_AGING_TIMER | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ALE_AGING_TIMER | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PRESCALE_2_DISABLE | R/W | 0h | ALE Prescaler 2 Disable. When set will divide the aging interval by 1000. This bit is designed for device verification and should not be used in production software. Combination of PreScale1Disable and PreScale2Disable will divide the aging interval by 1,000,000 for test purposes. |
30 | PRESCALE_1_DISABLE | R/W | 0h | ALE Prescaler 1 Disable. When set will divide the aging interval by 1000. This bit is designed for device verification and should not be used in production software. Combination of PreScale1Disable and PreScale2Disable will divide the aging interval by 1,000,000 for test purposes. |
29-24 | RESERVED | R/W | X | |
23-0 | ALE_AGING_TIMER | R/W | 0h | ALE Aging Timer. |
CPSW_ALE_NXT_HDR is shown in Figure 12-844 and described in Table 12-1628.
Return to Summary Table.
The ALE Next Header is used to limit the IPv6 Next header or IPv4 Protocol values found in the IP header. It is enabled via the DEFLMTNXTHDR bit in the VLAN entry. All four IP_NXT_HDR0 to IP_NXT_HDR3 bits are compared when enabled, so if only one is required, set them all to the one value to be tested.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E01Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IP_NXT_HDR3 | IP_NXT_HDR2 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IP_NXT_HDR1 | IP_NXT_HDR0 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | IP_NXT_HDR3 | R/W | 0h | The IP_NXT_HDR3 is the forth protocol or next header compared when enabled. |
23-16 | IP_NXT_HDR2 | R/W | 0h | The IP_NXT_HDR2 is the third protocol or next header compared when enabled. |
15-8 | IP_NXT_HDR1 | R/W | 0h | The IP_NXT_HDR1 is the second protocol or next header compared when enabled. |
7-0 | IP_NXT_HDR0 | R/W | 0h | The IP_NXT_HDR0 is the first protocol or next header compared when enabled. |
CPSW_ALE_TBLCTL is shown in Figure 12-845 and described in Table 12-1630.
Return to Summary Table.
The ALE table control register is used to read or write that ALE table entries. After writing to this register any read or write to any ALE register will be stalled until the read or write operation completes.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TABLEWR | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TABLEIDX | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | TABLEWR | R/W | 0h | Table Write. This bit is used to write the table words to the lookup table. 0h = Table Read Operation is performed. The contents of the TABLEIDX bit will be read into the CPSW_ALE_TBLWx registers (where x = 0 to 2). 1h = Table write operation is performed. This will take the current contents from the CPSW_ALE_TBLWx registers and write them to the table at the specified TABLEIDX. |
30-6 | RESERVED | R/W | X | |
5-0 | TABLEIDX | R/W | 0h | The table index is used to determine which lookup table entry is read or written. |
CPSW_ALE_TBLW2 is shown in Figure 12-846 and described in Table 12-1632.
Return to Summary Table.
The ALE Table Word 2 is the most significant word of an ALE table entry.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TABLEWRD2 | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R/W | X | |
6-0 | TABLEWRD2 | R/W | 0h | Table Entry bits [71-64] |
CPSW_ALE_TBLW1 is shown in Figure 12-847 and described in Table 12-1634.
Return to Summary Table.
The ALE Table Word 1 is the middle word of an ALE table entry.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TABLEWRD1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TABLEWRD1 | R/W | 0h | Table Entry bits [63-32] |
CPSW_ALE_TBLW0 is shown in Figure 12-848 and described in Table 12-1636.
Return to Summary Table.
The ALE Table Word 0 is the least significant word of an ALE table entry.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E03Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TABLEWRD0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TABLEWRD0 | R/W | 0h | Table Entry bits [31-0] |
CPSW_Iy_ALE_PORTCTL0_y is shown in Figure 12-849 and described in Table 12-1638.
Return to Summary Table.
The ALE Port Control Register sets the port specific modes of operation.
Offset = 0003E040h + (y * 4h); where y = 0 to 1
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E040h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
Iy_REG_Py_BCAST_LIMIT | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Iy_REG_Py_MCAST_LIMIT | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Iy_REG_Py_DROP_DOUBLE_VLAN | Iy_REG_Py_DROP_DUAL_VLAN | Iy_REG_Py_MACONLY_CAF | Iy_REG_Py_DIS_PAUTHMOD | Iy_REG_Py_MACONLY | Iy_REG_Py_TRUNKEN | Iy_REG_Py_TRUNKNUM | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Iy_REG_Py_MIRROR_SP | RESERVED | Iy_REG_Py_NO_SA_UPDATE | Iy_REG_Py_NO_LEARN | Iy_REG_Py_VID_INGRESS_CHECK | Iy_REG_Py_DROP_UN_TAGGED | Iy_REG_Py_PORTSTATE | |
R/W-0h | R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | Iy_REG_P0_BCAST_LIMIT | R/W | 0h | Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive. If the counters decrement to zero, then further packets are rate limited until the next prescale pulse. Broadcast rate limiting is enabled by a non-zero value in this field. |
23-16 | Iy_REG_P0_MCAST_LIMIT | R/W | 0h | Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive. If the counters decrement to zero, then further packets are rate limited until the next prescale pulse. Multicast rate limiting is enabled by a non-zero value in this field.The Iy_REG_P0_MCAST_LIMIT bit field is the number of Multicast packets that will be forwaded per CPSW_ALE_PRESCALE time. |
15 | Iy_REG_P0_DROP_DOUBLE_VLAN | R/W | 0h | Drop Double VLAN. When set cause any received packet with double VLANs to be dropped. That is if there are two ctag or two stag fields in the packet it will be dropped. |
14 | Iy_REG_P0_DROP_DUAL_VLAN | R/W | 0h | Drop Dual VLAN. When set will cause any received packet with dual VLAN stag followed by ctag to be dropped. |
13 | Iy_REG_P0_MACONLY_CAF | R/W | 0h | Mac Only Copy All Frames. When set a Mac Only port will transfer all received good frames to the host. When clear a Mac Only port will transfer packets to the host based on ALE destination address lookup operation (which operates more like an Ethernet Mac). A Mac Only port is a port with Iy_REG_P0_MACONLY set. |
12 | Iy_REG_P0_DIS_PAUTHMOD | R/W | 0h | Disable Port authorization. When set will allow unknown addresses to arrive on a switch in authorization mode. It is intended for device to device network connection on ports which do not require MACSEC encryption. |
11 | Iy_REG_P0_MACONLY | R/W | 0h | MAC Only. When set enables this port be treated like a MAC port for the host. All traffic received is only sent to the host. The host must direct traffic to this port as the lookup engine will not send traffic to the ports with the Iy_REG_P0_MACONLY bit set and the Iy_REG_P0_NO_LEARN also set. If Iy_REG_P0_MACONLY bit is set and the Iy_REG_P0_NO_LEARN is not set, the host can send non-directed packets that can be sent to the destination of a MacOnly port. It is also possible that the host can broadcast to all ports including MacOnly ports in this mode. |
10 | Iy_REG_P0_TRUNKEN | R/W | 0h | Trunk Enable. This field is used to enable a port into a trunk. Any port can be used as a trunk port, any two or more ports with the Iy_REG_P0_TRUNKEN bit is set and having the same Iy_REG_P0_TRUNKNUM will be placed in the same trunk. There is no requirement for trunk ports to be adjacent. If all ports are enabled in the same trunk, no traffic can flow as traffic received within a trunk is never trasnmitted out the same trunk. If only a single port is a member of a trunk, it looks like a normal port with exception of entries in the look up table will be noted as a trunk entry. |
9-8 | Iy_REG_P0_TRUNKNUM | R/W | 0h | Trunk Number. This field is used as the trunk number when the Iy_REG_P0_TRUNKEN bit is also set. Ports with the same trunk number that have the Iy_REG_P0_TRUNKEN bit is also set will have traffic distributed within the trunk based on the result of the hash function descrived above. |
7 | Iy_REG_P0_MIRROR_SP | R/W | 0h | Mirror Source Port - This field enables the source port mirror option. When this bit is set any traffic received on the port with the Iy_REG_P0_MIRROR_SP bit set will have its received traffic also sent to the MIRROR_TOP port. |
6 | RESERVED | R/W | X | |
5 | Iy_REG_P0_NO_SA_UPDATE | R/W | 0h | No Source Address Update. When set will not update the source addresses for this port. |
4 | Iy_REG_P0_NO_LEARN | R/W | 0h | No Learn. When set will not learn the source addresses for this port. |
3 | Iy_REG_P0_VID_INGRESS_CHECK | R/W | 0h | VLAN Ingress Check. When set if a packet received is not a member of the VLAN, the packet will be dropped. |
2 | Iy_REG_P0_DROP_UN_TAGGED | R/W | 0h | If Drop Untagged. When set will drop packets without a VLAN tag. |
1-0 | Iy_REG_P0_PORTSTATE | R/W | 0h | Port State. Defins the current port state used for lookup operations. 0h = Disabled 1h = Blocked 2h = Learning 3h = Forwarding |
CPSW_ALE_UVLAN_MEMBER is shown in Figure 12-850 and described in Table 12-1640.
Return to Summary Table.
The ALE Unknown VLAN Member Mask Register is used to specify the member list for unknown VLAN ID.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | UVLAN_MEMBER_LIST | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1-0 | UVLAN_MEMBER_LIST | R/W | 0h | Unknown VLAN Member List. |
CPSW_ALE_UVLAN_URCAST is shown in Figure 12-851 and described in Table 12-1642.
Return to Summary Table.
The ALE Unknown VLAN Unregistered Multicast Flood Mask Register is used to specify which egress ports unregistered multicast addresses egress for the unregistered VLAN ID.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E094h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | UVLAN_UNREG_MCAST_FLOOD_MASK | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1-0 | UVLAN_UNREG_MCAST_FLOOD_MASK | R/W | 0h | Unknown VLAN Unregister Multicast Flood Mask. |
CPSW_ALE_UVLAN_RMCAST is shown in Figure 12-852 and described in Table 12-1644.
Return to Summary Table.
The ALE Unknown VLAN Registered Multicast Flood Mask Register is used to specify which egress ports registered multicast addresses egress for the unregistered VLAN ID.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E098h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | UVLAN_REG_MCAST_FLOOD_MASK | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1-0 | UVLAN_REG_MCAST_FLOOD_MASK | R/W | 0h | Unknown VLAN Register Multicast Flood Mask. |
CPSW_ALE_UVLAN_UNTAG is shown in Figure 12-853 and described in Table 12-1646.
Return to Summary Table.
The ALE Unknown VLAN force Untagged Egress Mask Register is used to specify which egress ports the VLAN ID will be removed.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E09Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | UVLAN_FORCE_UNTAGGED_EGRESS | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | 0h | |
1-0 | UVLAN_FORCE_UNTAGGED_EGRESS | R/W | 0h | Unknown VLAN Force Untagged Egress Mask. |
CPSW_ALE_STAT_DIAG is shown in Figure 12-854 and described in Table 12-1648.
Return to Summary Table.
The ALE Statistic Output Diagnostic Register allows the output statistics to diagnose the SW counters. This register is for diagnostic only.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E0B8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PBCAST_DIAG | RESERVED | PORT_DIAG | |||||
R/W-0h | R/W-X | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT_DIAG | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | |
15 | PBCAST_DIAG | R/W | 0h | When set and the PORT_DIAG is set to zero, will allow all ports to see the same stat diagnostic increment. |
14-9 | RESERVED | R/W | X | |
8 | PORT_DIAG | R/W | 0h | The port selected that a received packet will cause the selected error to increment |
7-4 | RESERVED | R/W | 0h | |
3-0 | STAT_DIAG | R/W | 0h | When non-zero will cause the selected statistic to increment on the next frame received. For the selected Port. 0h = Disabled 1h = Destination Equal Source Drop Stat will count 2h = VLAN Ingress Check Drop Stat will count 3h = Source Multicast Drop Stat will count 4h = Dual VLAN Drop Stat will count 5h = Ether Type length error Drop Stat will count 6h = Next Hop Limit Drop Stat will count 7h = IPv4 Fragment Drop Stat will count 8h = Classifier Hit Stat will count 9h = Classifier Red Drop Stat will count 10h = Classifier Yellow Drop Stat will count 11h = ALE Overflow Drop Stat will count 12h = Rate Limit Drop Stat will count 13h = Blocked Address Drop Stat will count 14h = Secure Address Drop Stat will count 15h = Authorization Drop Stat will count |
CPSW_ALE_OAM_LB_CTRL is shown in Figure 12-855 and described in Table 12-1650.
Return to Summary Table.
The ALE OAM Control allows ports to be put into OAM Loopback, only non-supervisor packet are looped back to the source port.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E0BCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OAM_LB_CTRL | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1-0 | OAM_LB_CTRL | R/W | 0h | The OAM_LB_CTRL bit field allows any port to be put into OAM loopback, that is any packet received will be returned to the same port with an CPSW_ALE_EGRESSOP[31-24] EGRESS_OP of 0xFF which swaps the source (SA) and destination address (DA). BPDUs will still flow through as normal so that OAM can be remotly requested and disabled. |
CPSW_ALE_MSK_MUX0 is shown in Figure 12-856 and described in Table 12-1652.
Return to Summary Table.
VLAN Mask Mux 0. The ALE Mask Mux 0 register is used along with the VLAN registered/unregistered index selectors from the Lookup Table to determine the value for VLAN registered and unregister mask respectively.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E0C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VLAN_MASK_MUX_0 | ||||||
R-X | R-3h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | X | |
1-0 | VLAN_MASK_MUX_0 | R | 3h | VLAN Mask Mux 0. |
CPSW_Ix_ALE_MSK_MUXx is shown in Figure 12-857 and described in Table 12-1654.
Return to Summary Table.
VLAN Mask Mux x (where x = 1 to 3). The ALE Mask Mux registers are used along with the VLAN registered/unregistered index selectors from the Lookup Table to determine the value for VLAN registered and unregister mask respectively.
Offset = 0003E0C4h + (x * 4h); where x = 1 to 3
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E0C4h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | I1_REG_VLAN_MASK_MUX_1 | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1-0 | Ix_REG_VLAN_MASK_MUX_x | R/W | 0h | VLAN Mask Mux x (where x = 1 to 3). |
CPSW_ALE_EGRESSOP is shown in Figure 12-858 and described in Table 12-1656.
Return to Summary Table.
The Egress Operation register allows enabled classifiers with IPSA or IPDA match to use the CPSW Egress Packet Operations Inter VLAN Routing sub functions. If the packet was destined for the host, but matches a clasifier that has a programmed egress opcode, it will be forwarded to the destination ports where the destination ports will use the thier egress opcode entry to modify the packet. InterVLAN Routing and mirroring need to be understood, they are orthogonal functions.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E0FCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
EGRESS_OP | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EGRESS_TRK | TTL_CHECK | RESERVED | |||||
R/W-0h | R/W-0h | R/W-X | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DEST_PORTS | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | EGRESS_OP | R/W | 0h | The Egress Operation defines the operation performed by the CPSW Egress Packet Operations 0h = NOP : 1-n: Defines which egress Operation will be performed. This allows Inter VLAN routing to be configured for high bandwidth traffic, reducing CPU load. FFh: Swaps source address (SA) and destination address (DA) of packet, this is intended to allow OAM diagnostics for a link. |
23-21 | EGRESS_TRK | R/W | 0h | The Egress Trunk Index is the calculated trunk index from the SA, DA or VLAN if modified to that InterVLAN routing will work on trunks as well. The DA, SA and VLAN are ignored for trunk generation on InterVLAN Routing so that this field is the index generated from the Egress Op replacements elclusive or'd together into a three bit index. |
20 | TTL_CHECK | R/W | 0h | The TTL Check will cause any packet that fails TTL checks to not be routed to the Inter VLAN Routing sub functions. The packet will be routed to the host it was destined to. |
19-2 | RESERVED | R/W | X | |
1-0 | DEST_PORTS | R/W | 0h | The Destination Ports is a list of the ports the classified packet will be set to. If a destination is a Trunk, all the port bits for that trunck must be set. |
CPSW_ALE_POLICECFG0 is shown in Figure 12-859 and described in Table 12-1658.
Return to Summary Table.
The Policing Config 0 holds the port, frame priority and ONU address index as well as match enables for port, frame priority and ONU address matching.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PORT_MEN | TRUNKID | RESERVED | PORT_NUM | RESERVED | |||
R/W-0h | R/W-0h | R/W-X | R/W-0h | R/W-X | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI_MEN | PRI_VAL | |||||
R/W-X | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ONU_MEN | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ONU_INDEX | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PORT_MEN | R/W | 0h | Port Match Enable. |
30 | TRUNKID | R/W | 0h | Trunk ID. |
29-26 | RESERVED | R/W | 0h | |
25 | PORT_NUM | R/W | 0h | Port Number. |
24-20 | RESERVED | R/W | 0h | |
19 | PRI_MEN | R/W | 0h | Priority Match Enable. |
18-16 | PRI_VAL | R/W | 0h | Priority Value. |
15 | ONU_MEN | R/W | 0h | OUI Match Enable. |
14-6 | RESERVED | R/W | 0h | |
5-0 | ONU_INDEX | R/W | 0h | OUI Table Entry Index. |
CPSW_ALE_POLICECFG1 is shown in Figure 12-860 and described in Table 12-1660.
Return to Summary Table.
The Policing Config 1 holds the match enable/match index for the L2 Destination and L2 source addresses.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E104h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DST_MEN | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DST_INDEX | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SRC_MEN | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRC_INDEX | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | DST_MEN | R/W | 0h | Destination Address Match Enable. |
30-22 | RESERVED | R/W | X | |
21-16 | DST_INDEX | R/W | 0h | Destination Address Table Entry Index. |
15 | SRC_MEN | R/W | 0h | Source Address Match Enable. |
14-6 | RESERVED | R/W | X | |
5-0 | SRC_INDEX | R/W | 0h | Source Address Table Entry Index. |
CPSW_ALE_POLICECFG2 is shown in Figure 12-861 and described in Table 12-1662.
Return to Summary Table.
The Policing Config 2 holds the match enable/match index for the Outer VLAN and Inner VLAN addresses.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E108h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
OVLAN_MEN | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | OVLAN_INDEX | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IVLAN_MEN | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IVLAN_INDEX | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | OVLAN_MEN | R/W | 0h | Outer VLAN Match Enable. |
30-22 | RESERVED | R/W | 0h | |
21-16 | OVLAN_INDEX | R/W | 0h | Outer VLAN Table Entry Index. |
15 | IVLAN_MEN | R/W | 0h | Inner VLAN Match Enable. |
14-6 | RESERVED | R/W | 0h | |
5-0 | IVLAN_INDEX | R/W | 0h | Inner VLAN Table Entry Index. |
CPSW_ALE_POLICECFG3 is shown in Figure 12-862 and described in Table 12-1664.
Return to Summary Table.
The Policing Config 3 holds the match enable/match index for the Ether Type and IP Source address.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E10Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ETHERTYPE_MEN | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ETHERTYPE_INDEX | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IPSRC_MEN | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IPSRC_INDEX | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ETHERTYPE_MEN | R/W | 0h | EtherType Match Enable. |
30-22 | RESERVED | R/W | X | |
21-16 | ETHERTYPE_INDEX | R/W | 0h | EtherType Table Entry Index. |
15 | IPSRC_MEN | R/W | 0h | IP Source Address Match Enable. |
14-6 | RESERVED | R/W | X | |
5-0 | IPSRC_INDEX | R/W | 0h | IP Source Address Table Entry Index. |
CPSW_ALE_POLICECFG4 is shown in Figure 12-863 and described in Table 12-1666.
Return to Summary Table.
The Policing Config 4 holds the match enable/match index for the IP Destination address
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E110h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
IPDST_MEN | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | IPDST_INDEX | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-X | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IPDST_MEN | R/W | 0h | IP Destination Address Match Enable. |
30-22 | RESERVED | R/W | X | |
21-16 | IPDST_INDEX | R/W | 0h | IP Destination Address Table Entry Index. |
15-0 | RESERVED | R/W | X |
CPSW_ALE_POLICECFG6 is shown in Figure 12-864 and described in Table 12-1668.
Return to Summary Table.
The PIR counter is a 37 bit internal counter where PIR_IDLE_INC_VAL is added every clock and the frame size << 18 is subtracted at EOF if not RED at LUT time. If the counter is negative the packet will be marked RED, else it can be YELLOW or GREEN based on the CIR counter. If only this counter is used (CIR_IDLE_INC_VAL = 0h), then packets are marked RED or GREEN based on PIR counter only.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E118h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PIR_IDLE_INC_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PIR_IDLE_INC_VAL | R/W | 0h | Peak Information Rate Idle Increment Value. |
CPSW_ALE_POLICECFG7 is shown in Figure 12-865 and described in Table 12-1670.
Return to Summary Table.
The CIR counter is a 37 bit internal counter where CIR_IDLE_INC_VAL is added every clock and the frame size << 18 is subtracted at EOF if not RED or YELLOW at LUT time. If the counter is positive the packet will be marked GREEN, else it can be YELLOW or RED based on the PIR counter. If only this counter is used (PIR_IDLE_INC_VAL= 0h), then packets are marked YELLOW or GREEN based on CIR counter only.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E11Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CIR_IDLE_INC_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CIR_IDLE_INC_VAL | R/W | 0h | Committed Information Idle Increment Value - The number added to the CIR counter every clock cycle. If zero the CIR counter is disabled and packets will never be marked or processed as YELLOW. |
CPSW_ALE_POLICETBLCTL is shown in Figure 12-866 and described in Table 12-1672.
Return to Summary Table.
The Policing Table Control is used to read or write the selected policing/classifier entry. The selected policing/classifier entry is only read or written after this register is written based on the value of the WRITE_ENABLE bit.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E120h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
WRITE_ENABLE | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | POL_TBL_IDX | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | WRITE_ENABLE | R/W | 0h | Write Enable. |
30-3 | RESERVED | R/W | X | |
2-0 | POL_TBL_IDX | R/W | 0h | Policer Entry Index. |
CPSW_ALE_POLICECONTROL is shown in Figure 12-867 and described in Table 12-1674.
Return to Summary Table.
The Control Enables color marking as well as internal ALE packet dropping rules.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E124h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
POLICING_EN | RESERVED | RED_DROP_EN | YELLOW_DROP_EN | RESERVED | YELLOWTHRESH | ||
R/W-0h | R/W-X | R/W-0h | R/W-0h | R/W-X | R/W-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
POLMCHMODE | PRIORITY_THREAD_EN | MAC_ONLY_DEF_DIS | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-X | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-X | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | POLICING_EN | R/W | 0h | Policing Enable - Enables the policing to color the packets, this also enables red or yellow drop capabilities. |
30 | RESERVED | R/W | X | |
29 | RED_DROP_EN | R/W | 0h | RED Drop Enable - Enables the ALE to drop the red colored packets. |
28 | YELLOW_DROP_EN | R/W | 0h | WELLOW Drop Enable - Enables the ALE to drop yellow packets based on the YELLOWTHRESH bit value. This field would normally not be used as to let the switch drop packets at a buffer threshold instead. In the event that the switch does not enable buffer threshold dropping, YELLOW packets can be dropped based on this feature. |
27 | RESERVED | R/W | 0h | |
26-24 | YELLOWTHRESH | R/W | 0h | Yellow Threshold - When set enables a portion of the yellow packets to be dropped based on the YELLOW_DROP_EN bit enable. 0h = 100% 1h =50% 2h = 33% 3h = 25% 4h = 20% 5h = 17% 6h = 14% 7h = 13% |
23-22 | POLMCHMODE | R/W | 0h | Policing Match Mode - This field determines what happens to packets that fail to hit any policing/classifier entry. 0h = No Hit packets are marked GREEN 1h = No Hit packets are marked YELLOW 2h = No Hit packets are marked RED 3h = No Hit packets are marked based on policing/classifier entry=0 state. |
21 | PRIORITY_THREAD_EN | R/W | 0h | Priority Thread Enable - This field determines if priority is OR'd to the default thread when no classifiers hit and the default thread is enabled. |
20 | MAC_ONLY_DEF_DIS | R/W | 0h | MAC Only Default Disable - This field when set disables the default thread on MAC Only Ports. That is the default thread will be {port,priority}. If the traffic matches a classifier with a thread mapping, the classifier thread mapping still occurs. |
19-0 | RESERVED | R/W | X |
CPSW_ALE_POLICETESTCTL is shown in Figure 12-868 and described in Table 12-1676.
Return to Summary Table.
The Policing Test Control enables the ability to determine which policing entry has been hit and whether they reported a red or yellow rate condition.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E128h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
POL_CLRALL_HIT | POL_CLRALL_REDHIT | POL_CLRALL_YELLOWHIT | POL_CLRSEL_ALL | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-X | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | POL_TEST_IDX | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | POL_CLRALL_HIT | R/W | 0h | Policer Clear - This bit clears all the policing/classifier hit bits. This bit is self clearing. This can be used to test the fact that a policing/classifier entry has been hit. |
30 | POL_CLRALL_REDHIT | R/W | 0h | Policer Clear RED - This bit clears all the policing/classifier RED hit bits. This bit is self clearing. This can be used to test the fact that a policing/classifier entry has been hit during a RED condition. |
29 | POL_CLRALL_YELLOWHIT | R/W | 0h | Policer Clear YELLOW - This bit clears all the policing/classifier YELLOW hit bits. This bit is self clearing. This can be used to test the fact that a policing/classifier entry has been hit during a YELLOW condition. |
28 | POL_CLRSEL_ALL | R/W | 0h | Police Clear Selected - This bit clears the selected policing/classifier hit, redhit and yellowhit bits. This bit is self clearing. |
27-3 | RESERVED | R/W | X | |
2-0 | POL_TEST_IDX | R/W | 0h | Policer Test Index - This field selects which policing/classifier hit bits will be read or written. |
CPSW_ALE_POLICEHSTAT is shown in Figure 12-869 and described in Table 12-1678.
Return to Summary Table.
The policing hit status is a read only register that reads the hit bits of the selected policing/classifier.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E12Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
POL_HIT | POL_REDHIT | POL_YELLOWHIT | RESERVED | ||||
R-0h | R-0h | R-0h | R-X | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-X | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | POL_HIT | R | 0h | Policer Hit. |
30 | POL_REDHIT | R | 0h | Policer Hit RED. |
29 | POL_YELLOWHIT | R | 0h | Policer Hit YELLOW. |
28-0 | RESERVED | R | X |
CPSW_ALE_THREADMAPDEF is shown in Figure 12-870 and described in Table 12-1680.
Return to Summary Table.
The THREAD Mapping Default Value register is used to set the default thread ID when no classifier is matched.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E134h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DEFTHREAD_EN | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DEFTHREADVAL | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | DEFTHREAD_EN | R/W | 0h | Default Tread Enable. |
14-6 | RESERVED | R/W | X | |
5-0 | DEFTHREADVAL | R/W | 0h | Default Thread Value. |
CPSW_ALE_THREADMAPCTL is shown in Figure 12-871 and described in Table 12-1682.
Return to Summary Table.
The THREAD Mapping Control register allows the highest matched classifier to return a particular thread ID for traffic sent to the host. This allows particular classifier matched traffic to be placed an a particular hosts queue.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E138h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLASSINDEX | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | X | |
2-0 | CLASSINDEX | R/W | 0h | Classifier Index. |
CPSW_ALE_THREADMAPVAL is shown in Figure 12-872 and described in Table 12-1684.
Return to Summary Table.
The THREAD Mapping Value register is used to set the thread ID for a particular classifier entry.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_ALE | 4603 E13Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
THREAD_EN | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | THREADVAL | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | THREAD_EN | R/W | 0h | Thread Enable. |
14-6 | RESERVED | R/W | X | |
5-0 | THREADVAL | R/W | 0h | Thread Value. |