SPRUIZ2 july   2023 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F2838x and F28P65x
    1. 1.1 F2838x and F28P65x Feature Comparison
  5. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 176-Pin PTP Package
    2. 2.2 Use of Existing 176-Pin F2838x PCB Design
      1.      9
      2. 2.2.1 JTAG TRSTn No-Connect
      3. 2.2.2 GPIO Input Buffer Control Register
      4. 2.2.3 176-Pin GPIO Pin/Multiplex and ADCD Considerations
        1. 2.2.3.1 176-Pin PTP Pins With Different GPIO Assignment
        2. 2.2.3.2 ADCD Channel Migration
    3. 2.3 176-Pin PTP New PCB Design
    4. 2.4 337-BGA ZWT Application to 256-BGA ZEJ or 169-BGA NMR
  6. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28P65x
      1. 3.1.1  Lock-step Compare Module (LCM)
      2. 3.1.2  Expanded Analog Channels
      3. 3.1.3  Firmware Update (FWU)
      4. 3.1.4  Flexible GPIO and Digital Input Pins
      5. 3.1.5  New ADC Features
      6. 3.1.6  New EPWM Features
      7. 3.1.7  New CMPSS Features
      8. 3.1.8  ADC Hardware Redundancy Safety Checker
      9. 3.1.9  Flexible Memory Sharing between CPU Subsystems
      10. 3.1.10 Increased RAM Program Memory on CLA
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 PIE Channel Mapping
        1. 3.5.1.1 F2838x vs F28P65x PIE Channel Mapping Comparison
      2. 3.5.2 Bootrom
      3. 3.5.3 CLB and Motor Control Libraries
      4. 3.5.4 ERAD
      5. 3.5.5 AGPIO Filter
    6. 3.6 Power Management
      1. 3.6.1 VREGENZ
      2. 3.6.2 LDO/VREG
      3. 3.6.3 POR/BOR
      4. 3.6.4 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
      1. 3.8.1 F2838x vs F28P65x GPIO Mux Comparison
    9. 3.9 Analog Multiplexing Changes
      1. 3.9.1 F2838x_176PTP vs F28P65x_176PTP Analog Connections Comparison
  7. 4Application Code Migration From F2838x to F28P65x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  8. 5References

3.4 Analog Module Differences

This section outlines the analog differences between F2838x and F28P65x. The ADC on F28P65x has a lot of new features compared to the ADC on F2838x. Table 3-3 shows the differences.

Table 3-3 Analog Module Differences
Module Category F2838x F28P65x Notes
ASUBSYS Registers ANAREFTRIMD - Analog Reference Trim D Register
- ANAREFCTL Analog Reference Control Register
- VMONCTL Voltage Monitor Control Register
- CMPHPMXSEL Comparator High Positive Mux Select Register
- CMPLPMXSEL Comparator Low Positive Mux Select Register
- CMPHNMXSEL Comparator High Negative Mux Select Register
- CMPLNMXSEL Comparator Low Negative Mux Select Register
- ADCDACLOOPBACK DAC to ADC Loopback Register
- AGPIOCTRLG AGPIO Control Register
- AGPIOCTRLH AGPIO Control Register
- CMPHPMXSEL1 Comparator High Positive Mux Select Register
- CMPLPMXSEL1 Comparator Low Positive Mux Select Register
- ADCSOCFRCGB ADC Global SOC Force Register
- ADCSOCFRCGBSEL ADC Global SOC Force Select Register
LOCK Additional Lock Fields for New Registers in F28P65x
ADC(1) Number 4 - ADCA to ADCD 3 - ADCA to ADCC
Max Speed 50 MHz
Registers - ADCCTL1.EXTMUXPRESELECTEN External Mux Preselect Enable
- ADCCTL1.TDMAEN Enable Alternate DMA Timings
- ADCCTL2.OFFTRIMMODE Offset Trim Mode
ADCBURSTCTL.BURSTTRIGSEL[5..0] ADCBURSTCTL.BURSTTRIGSEL[6..0]
- ADCINTFLG.ADCINTxRESULT ADC Interrupt Results Ready
ADCINTFLGCLR Clears respective flag bit in ADCINTFLG register on F28P65x
ADCINTSEL1N2.INT1SEL[3..0] ADCINTSEL1N2.INT1SEL[4..0] New OSINT Options on F28P65x
ADCINTSEL1N2.INT2SEL[3..0] ADCINTSEL1N2.INT2SEL[4..0]
ADCINTSEL3N4.INT1SEL[3..0] ADCINTSEL3N4.INT1SEL[4..0]
ADCINTSEL3N4.INT2SEL[3..0] ADCINTSEL3N4.INT2SEL[4..0]
ADCSOCxCTL.CHSEL[18..15] ADCSOCxCTL.CHSEL[19..15]
ADCSOCxCTL.TRIGSEL[25..20] ADCSOCxCTL.TRIGSEL[26..20]
- ADCSOCxCTL.EXTCHSEL SOC External Channel Mux Select
ADCOFFTRIM.OFFTRIM F28P65x - ADC Offset Trim 12B SE Even
- ADCOFFTRIM.OFFTRIM12BSEODD ADC Offset Trim 12B SE Odd
- ADCPPBxCONFIG.ABSEN ADC Post Processing Block Absolute Enable
ADCPPBxOFFCAL F28P65x - OFFCAL of the lowest numbered PPB will be applied if multiple PPBs point to the same SOC.
ADCPPBxTRIPHI.LIMITHI[15..0] ADCPPBxTRIPHI.LIMITHI[23..0]
ADCPPBxTRIPHI.HSIGN - High Limit Sign Bit
- ADCPPBxTRIPLO.LIMITLO2EN Extended Low Limit 2 Enable
ADC(1) Registers ADCPPBxRESULT Updates related to ADCINTFLG on F28P65x
- ADCOFFTRIM2 ADC Offset Trim Register
- ADCOFFTRIM3 ADC Offset Trim Register
- ADCSAFECHECKRESEN ADC Safe Check Result Enable Register
- ADCREV2 ADC Wrapper Revision Register
- REPxCTL ADC Trigger Repeater Control Register
- REPxN ADC Trigger Repeater N Select Register
- REPxPHASE ADC Trigger Repeater Phase Select Register
- REPxSPREAD ADC Trigger Repeater Spread Select Register
- REPxFRC ADC Trigger Repeater Software Force Register
- ADCPPBxLIMIT ADC PPB Conversion Count Limit Register
- ADCPPBPxPCOUNT ADC PPB Partial Conversion Count Register
- ADCPPBxCONFIG2 ADC PPB Sum Shift Register
- ADCPPBxPSUM ADC PPB Partial Sum Register
- ADCPPBxPMAX ADC PPB Partial Max Register
- ADCPPBxPMAXI ADC PPB Partial Max Index Register
- ADCPPBxPMIN ADC PPB Partial Min Register
- ADCPPBxPMINI ADC PPB Partial Min Index Register
- ADCPPBxTRIPLO2 ADC PPB Extended Trip Low Register
- ADCPPBxSUM ADC PPB Final Sum Result Register
- ADCPPBxCOUNT ADC PPB Final Conversion Count Register
- ADCPPBxMAX ADC PPB Final Max Result Register
- ADCPPBxMAXI ADC PPB Final Max Index Result Register
- ADCPPBxMIN ADC PPB Final Min Result Register
- ADCPPBxMINI ADC PPB Final Min Index Result Register
- ADC_SAFECHECK_REGS ADC Safety Check Registers
- ADC_SAFECHECK_INTEVT_REGS ADC Safety Check Interrupt & Event Registers
GPDAC Number 3 - GPDACA, GPDACB, GPDACC 2 - GPDACA, GPDACC
Registers - DACCTL.MODE Gain Mode Select
DACCTL.SYNCSEL[7..4] DACCTL.SYNCSEL[8..4]
CMPSS (1) Number 8 - CMPSS1 to CMPSS8 11 - CMPSS1 to CMPSS11
Registers - COMPDACHCTL.RAMPDIR High Ramp Generator Direction
COMPDACCTL COMPDACHCTL Name change on F28P65x to accommodate dual up/down ramp generators.
RAMPMAXREFA RAMPHREFA
RAMPMAXREFA.RAMPMAXREF RAMPHREFA.RAMPHREF
RAMPMAXREFS RAMPHREFS
RAMPMAXREFS.RAMPMAXREF RAMPHREFS.RAMPHREF
RAMPDECVALA RAMPHSTEPVALA
RAMPDECVALA.RAMPDECVAL RAMPHSTEPVALA.RAMPHSTEPVAL
RAMPDECVALS RAMPHSTEPVALS
RAMPDECVALS.RAMPDECVAL RAMPHSTEPVALS.RAMPHSTEPVAL
RAMPSTS RAMPHSTS
RAMPSTS.RAMPVALUE RAMPHSTS.RAMPHVALUE
CTRIPxFILCLKCTL.CLKPRESCALE[9..0] CTRIPxFILCLKCTL.CLKPRESCALE[15..0] CMPSS filter prescaling size increased on F28P65x
CTRIPxFILCTL.SAMPWIN[8..4] CTRIPxFILCTL.SAMPWIN[8..3] CMPSS filter sample window size increased on F28P65x
CTRIPxFILCTL.THRESH[13..9] CTRIPxFILCTL.THRESH[14..9] CMPSS filter threshold size increased on F28P65x
- CTRIPxFILCTL.FILTINSEL Filter input mux select
- COMPDACHCTL2 CMPSS High DAC Control Register 2
- RAMPHCTLA CMPSS High Ramp Control Active Register
- RAMPHCTLS CMPSS High Ramp Control Shadow Register
- DACHVALS2 CMPSS High DAC Value Shadow Register 2
- DACLVALS2 CMPSS Low DAC Value Shadow Register 2
- COMPDACLCTL CMPSS Low DAC Control Register
- COMPDACLCTL2 CMPSS Low DAC Control Register 2
- RAMPLREFA CMPSS Low Ramp Reference Active Register
- RAMPLREFS CMPSS Low Ramp Reference Shadow Register
- RAMPLSTEPVALA CMPSS Low Ramp Step Value Active Register
- RAMPLCTLA CMPSS Low Ramp Control Active Register
- RAMPLSTEPVALS CMPSS Low Ramp Step Value Shadow Register
CMPSS (1) Registers - RAMPLCTLS CMPSS Low Ramp Control Shadow Register
- RAMPLSTS CMPSS Low Ramp Status Register
- RAMPLDLYA CMPSS Low Ramp Delay Active Register
- RAMPLDLYS CMPSS Low Ramp Delay Shadow Register
- CTRIPLFILCLKCTL2 CTRIPL Filter Clock Control Register 2
- CTRIPHFILCLKCTL2 CTRIPH Filter Clock Control Register 2
Temp Sensor Number 1 - (in ADCA ch 13) 1 - (in ADCB ch 18)
(1) In porting software from F2838x to F28P65x (or the other way around), care must be taken to ensure that the correct ADC channels are used because of a difference in channel assignment, see Section 3.9.