SPRUJ63A September   2022  – October 2023

 

  1.   1
  2.   Trademarks
  3. 1Introduction
    1. 1.1 EVM Revisions and Assembly Variants
    2. 1.2 Inside the Box
  4. 2Important Usage Notes
    1. 2.1 Power-On Usage Note
    2. 2.2 EMC, EMI, and ESD Compliance
  5. 3System Description
    1. 3.1 Key Features
    2. 3.2 Functional Block Diagram
    3. 3.3 Power-On/Off Procedures
      1. 3.3.1 Power-On Procedure
      2. 3.3.2 Power-Off Procedure
    4. 3.4 Peripheral and Major Component Description
      1. 3.4.1  Clocking
        1. 3.4.1.1 Ethernet PHY Clock
        2. 3.4.1.2 AM64x/AM243x Clock
        3. 3.4.1.3 PCIe Clock
      2. 3.4.2  Reset
      3. 3.4.3  Power
        1. 3.4.3.1 Power Input
        2. 3.4.3.2 Reverse Polarity Protection
        3. 3.4.3.3 Current Monitoring
        4. 3.4.3.4 Power Supply
        5. 3.4.3.5 Power Sequencing
        6. 3.4.3.6 AM64x/AM243x Power
      4. 3.4.4  Configuration
        1. 3.4.4.1 Boot Modes
      5. 3.4.5  JTAG
      6. 3.4.6  Test Automation
      7. 3.4.7  UART Interfaces
      8. 3.4.8  Memory Interfaces
        1. 3.4.8.1 DDR4 Interface
        2. 3.4.8.2 MMC Interfaces
          1. 3.4.8.2.1 Micro SD Interface
          2. 3.4.8.2.2 eMMC Interface
        3. 3.4.8.3 OSPI Interface
        4. 3.4.8.4 SPI EEPROM Interface
        5. 3.4.8.5 Board ID EEPROM Interface
      9. 3.4.9  Ethernet Interface
        1. 3.4.9.1 DP83867 PHY Default Configuration
        2. 3.4.9.2 DP83869 PHY Default Configuration
        3. 3.4.9.3 Ethernet LED
      10. 3.4.10 Display Interface
      11. 3.4.11 USB 2.0 Interface
      12. 3.4.12 PCIe Interface
      13. 3.4.13 High Speed Expansion Interface
      14. 3.4.14 CAN Interface
      15. 3.4.15 Interrupt
      16. 3.4.16 ADC Interface
      17. 3.4.17 Safety Connector
      18. 3.4.18 SPI Interfaces
      19. 3.4.19 I2C Interfaces
      20. 3.4.20 FSI Interface
  6. 4Known Issues and Modifications
    1. 4.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS
    2. 4.2 Issue 2 - DC Barrel Jack Warning when Hot-Plugging
    3. 4.3 Issue 3 - uSD Card Boot Not Working
  7. 5References
  8. 6Revision History

3.4.12 PCIe Interface

The Serdes0 interface of AM64x/AM243x is used to implement a x1 lane PCIe interface with the signals routed to a x4 PCIe slot connector. PCIE-064-02-F-D-TH connector from Samtec is be used for the PCIe interface and this connector meets the PCIe CEM v2.0 specification both physically and electrically. PCIE-064-02-F-D-TH connector is designed to support a 25 W slot including 2.1A for the 12 V rail and 3 A for the 3.3 V rail. The PCIe interface is designed to support either root complex operation or endpoint operation with a cross over cable. SoC_I2C1 is used for control purpose. The link activation signal from PCIe connectors is pulled up to VCC3V3_SYS.

Clock: SERDES REFCLK is routed to the PCIe REF CLK pins to allow either receiving or providing a clock from the connector (no separate PLL to generate PCIe REF CLK available on the EVM).

Hot plug: The PRSNT1# and PRSNT2# signals are the hot plug presence detect signals. The PRSNT2# is pulled up and PRSNT1# is connected to ground so that PRSNT2# is pulled low when a daughter card is plugged in. A 3 pin header (J35) is provided to choose between RC and EP mode.

Reset: A 3 pin header (J34) is provided to select the reset source for host and endpoint PCIe operation. In case of host mode, PCIe_RST_OUT signal from IO Expander and RESETSTATz signal from SoC are ANDed and the output is connected to PCIe connector through 3 pin header. A jumper is mounted for the connectivity. Whereas in case of PCIe end point operation, the AM64x SoC receives reset signal from the add-on card and passed on to the MCU_PORz pin. The reset signal is connected to 3 pin header and the selection needs to be made with a jumper.

The PCIe x4 Connector JTAG signals are unused and test points are provided on the signals.

Table 3-22 describes the jumper options used to select if the EVM operates in Root Complex mode or in End Point mode.

Table 3-22 PCIe Jumper Options to Enable Root Complex and Endpoint Mode
Root ComplexEnd Point
1x3 header J34 and J35Short 1 and 2Short 2 and 3
GUID-A3A98A71-F982-48DC-9B7C-5D106C1332B2-low.pngFigure 3-25 AM64x/AM243x PCIe Interface
Table 3-23 PCIe Connector (J27) Pin-out
Pin No.Side A of PCIe ConnectorGP Board SignalSide B of PCIe ConnectorGP Board Signal
1PRSNT1#J35.3+12VVDD_12V
2+12VVDD_12V+12VVDD_12V
3+12VVDD_12V+12VVDD_12V
4GNDGROUNDGNDGROUND
5JTAG2TPSMCLKSoC_I2C1_CLK
6JTAG3TPSMDATASoC_I2C1_SDA
7JTAG4TPGNDGROUND
8JTAG5TP+3V3VCC3V3_SYS
9+3V3VCC3V3_SYSJTAG1TP
10+3V3VCC3V3_SYS3V3 VAUXVCC3V3_SYS
11PERST#J24.2WAKE#Pulled up to VCC3V3_SYS
12GNDGROUNDRSVD4Pulled up to VCC3V3_SYS
13REFCLK+SERDES_REFCLK0PGNDGROUND
14REFCLK-SERDER_REFCLK0NPETp0SERDES_TXP0
15GNDGROUNDPETn0SERDES_TXN0
16PERp0SERDES_RXP0GNDGND
17PERn0SERDES_RXN0PRSNT2#_1J35.2
18GNDGROUNDGNDGROUND
19RSVD1NCPETp1NC
20GNDGROUNDPETn1NC
21PERp1NCGNDGROUND
22PERn1NCGNDGROUND
23GNDGROUNDPETp2NC
24GNDGROUNDPETn2NC
25PERp2NCGNDGROUND
26PERn2NCGNDGROUND
27GNDGROUNDPETp3NC
28GNDGROUNDPETn3NC
29PERp3NCGNDGROUND
30PERn3NCRSVD3NC
31GNDGROUNDPRSNT2#_2NC
32RSVD2NCGNDGROUND