SPRUJ63A September   2022  – October 2023

 

  1.   1
  2.   Trademarks
  3. 1Introduction
    1. 1.1 EVM Revisions and Assembly Variants
    2. 1.2 Inside the Box
  4. 2Important Usage Notes
    1. 2.1 Power-On Usage Note
    2. 2.2 EMC, EMI, and ESD Compliance
  5. 3System Description
    1. 3.1 Key Features
    2. 3.2 Functional Block Diagram
    3. 3.3 Power-On/Off Procedures
      1. 3.3.1 Power-On Procedure
      2. 3.3.2 Power-Off Procedure
    4. 3.4 Peripheral and Major Component Description
      1. 3.4.1  Clocking
        1. 3.4.1.1 Ethernet PHY Clock
        2. 3.4.1.2 AM64x/AM243x Clock
        3. 3.4.1.3 PCIe Clock
      2. 3.4.2  Reset
      3. 3.4.3  Power
        1. 3.4.3.1 Power Input
        2. 3.4.3.2 Reverse Polarity Protection
        3. 3.4.3.3 Current Monitoring
        4. 3.4.3.4 Power Supply
        5. 3.4.3.5 Power Sequencing
        6. 3.4.3.6 AM64x/AM243x Power
      4. 3.4.4  Configuration
        1. 3.4.4.1 Boot Modes
      5. 3.4.5  JTAG
      6. 3.4.6  Test Automation
      7. 3.4.7  UART Interfaces
      8. 3.4.8  Memory Interfaces
        1. 3.4.8.1 DDR4 Interface
        2. 3.4.8.2 MMC Interfaces
          1. 3.4.8.2.1 Micro SD Interface
          2. 3.4.8.2.2 eMMC Interface
        3. 3.4.8.3 OSPI Interface
        4. 3.4.8.4 SPI EEPROM Interface
        5. 3.4.8.5 Board ID EEPROM Interface
      9. 3.4.9  Ethernet Interface
        1. 3.4.9.1 DP83867 PHY Default Configuration
        2. 3.4.9.2 DP83869 PHY Default Configuration
        3. 3.4.9.3 Ethernet LED
      10. 3.4.10 Display Interface
      11. 3.4.11 USB 2.0 Interface
      12. 3.4.12 PCIe Interface
      13. 3.4.13 High Speed Expansion Interface
      14. 3.4.14 CAN Interface
      15. 3.4.15 Interrupt
      16. 3.4.16 ADC Interface
      17. 3.4.17 Safety Connector
      18. 3.4.18 SPI Interfaces
      19. 3.4.19 I2C Interfaces
      20. 3.4.20 FSI Interface
  6. 4Known Issues and Modifications
    1. 4.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS
    2. 4.2 Issue 2 - DC Barrel Jack Warning when Hot-Plugging
    3. 4.3 Issue 3 - uSD Card Boot Not Working
  7. 5References
  8. 6Revision History

3.4.4.1 Boot Modes

The boot mode for the EVM is defined by either a bank of switches SW2 and SW3 or by the I2C buffer (U96) connected to the test automation connector (J38). All the boot mode pins have a weak pull-down resistor and a switch capable of connecting to a strong pull up resistor. Switch set to “ON” corresponds to logic “HIGH” while “OFF” corresponds to logic “LOW”.

For a full description of all AM64x SoC supported bootmodes, see the AM64x Sitara™ Processors Data Manual and AM64x Processors Silicon Revision 1.0 Texas Instruments Families of Products Technical Reference Manual.

The following boot modes are supported by EVM (and subject to change):

  1. OSPI
  2. MMC1 - SD Card
  3. MMC0 - eMMC installed
  4. USB - boot using host mode with bulk storage. USB 2.0 mass storage using FAT16/32 (thumb drive)
  5. USB - device boot DFU
  6. UART
  7. No-Boot

GUID-3B7E431B-B217-4400-921B-0195F0FAAA88-low.pngFigure 3-9 AM64x/AM243x EVM Schematic Excerpt, Boot Mode Selection Switches (SW2, SW3)
GUID-77FDDE91-9CCF-4A88-9D8F-8F9F076388D3-low.pngFigure 3-10 AM64x/AM243xEVM PCB, Boot Mode Selection Switches (SW2, SW3)

The BOOTMODE pins provide means to select the boot mode before the device is powered up. The pins are divided into the following categories:

Note: The following bit pattern is reversed in the table from the switch order.
Table 3-7 BOOTMODE Bits
Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10 Bit 9Bit 8Bit 7 Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1 Bit 0
RSVDRSVDBackup Boot Mode ConfigBackup Boot ModePrimary Boot Mode ConfigPrimary Boot ModePLL Config

BOOTMODE[2:0] - Denote system clock frequency for PLL configuration. By default, these bits are set for 25 MHz.

Table 3-8 PLL Reference Clock Selection BOOTMODE[2:0]
SW2.3SW2.2SW2.1PLL REF CLK (MHz)
offoffoff19.2
offoffon20
offonoff24
offonon25
onoffoff26
onoffon27
ononoffRSVD
onononRSVD

BOOTMODE[6:3] - This provides primary boot mode configuration to select the requested boot mode after POR, that is, the peripheral/memory to boot from.

Table 3-9 Boot Device Selection BOOTMODE[6:3]
SW2.7SW2.6SW2.5SW2.4Primary Boot Device Selected
offoffoffoffRSVD
offoffoffonOSPI
offoffonoffQSPI
offoffononSPI
offonoffoffRSVD
offonoffonRSVD
offononoffI2C
offonononUART
onoffoffoffMMC/SD Card
onoffoffoneMMC
onoffonoffUSB
onoffononGPMC NAND
ononoffoffGPMC NOR
ononoffonPCIe
onononoffxSPI
ononononNo-boot / Dev-boot

BOOTMODE[9:7] - These pins provide optional settings and are used in conjunction with the primary boot device selected. For more details, see the device-specific TRM.

Table 3-10 Primary Boot Media Configuration BOOTMODE[9:7]
SW3.2SW3.1SW2.8Primary Boot Device
RSVDRSVDRSVDRSVD
RSVDIclkCselOSPI
RSVDIclkCselQSPI
RSVDModeCselSPI
RSVDRSVDRSVDRSVD
RSVDRSVDRSVDRSVD
Bus ResetDon't CareAddrI2C
RSVDRSVDRSVDUART
PortRSVDFs/rawMMC / SD Card
RSVDRSVDRSVDeMMC
Core VoltModeLane SwapUSB
RSVDRSVDRSVDGPMC NAND
RSVDRSVDRSVDGPMC NOR
RSVDRSVDRSVDPCIe
SFDPRead CmdModexSPI
RSVDRSVDRSVDNo-boot / Dev-boot

BOOTMODE[12:10] - Select the backup boot mode, that is, the peripheral/memory to boot from, if primary boot device failed.

Table 3-11 Backup Boot Mode Selection BOOTMODE[12:10]
SW3.2SW3.1SW2.8Backup Boot Device Selected
offoffoffNone (No backup mode)
offoffonUSB
offonoffRSVD
offononUART
onoffoffRSVD
onoffonMMC/SD
ononoffSPI
onononI2C

BOOTMODE[13] - These pins provide optional settings and are used in conjunction with the backup boot device devices. For more details on bit details, see the device-specific TRM. When on, switches SW3.6 sets 1 and, when off, sets 0.

Table 3-12 Backup Boot Media Configuration BOOTMODE[13]
SW3.6Boot Device
RSVDNone
ModeUSB
RSVDRSVD
RSVDUART
RSVDRSVD
PortMMC/SD
RSVDSPI
RSVDI2C

BOOTMODE[14:15] - Reserved.