SWCU194 March   2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1 Target Applications
    2. 1.2 Overview
    3. 1.3 Functional Overview
      1. 1.3.1  ArmCortex-M33 with FPU
        1. 1.3.1.1 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block (SCB)
      2. 1.3.2  On-Chip Memory
        1. 1.3.2.1 SRAM
        2. 1.3.2.2 Flash Memory
        3. 1.3.2.3 ROM
      3. 1.3.3  Radio
      4. 1.3.4  Security Core
      5. 1.3.5  Runtime Security
      6. 1.3.6  General-Purpose Timers
        1. 1.3.6.1 Watchdog Timer
        2. 1.3.6.2 Always-On Domain
      7. 1.3.7  Direct Memory Access
      8. 1.3.8  System Control and Clock
      9. 1.3.9  Serial Communication Peripherals
        1. 1.3.9.1 UART
        2. 1.3.9.2 I2C
        3. 1.3.9.3 I2S
        4. 1.3.9.4 SPI
      10. 1.3.10 Programmable I/Os
      11. 1.3.11 Sensor Controller
      12. 1.3.12 Random Number Generator
      13. 1.3.13 cJTAG and JTAG
      14. 1.3.14 Power Supply System
        1. 1.3.14.1 Supply System
          1. 1.3.14.1.1 VDDS
          2. 1.3.14.1.2 VDDR
          3. 1.3.14.1.3 Digital Core Supply
          4. 1.3.14.1.4 Other Internal Supplies
        2. 1.3.14.2 DC/DC Converter
  3. 2  Arm Cortex-M33 Processor with FPU
    1. 2.1 Arm Cortex-M33 Processor Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Integrated Configurable Debug
      2. 2.3.2 Trace Port Interface Unit
      3. 2.3.3 Arm Cortex-M33 System Peripheral Details
        1. 2.3.3.1 Floating Point Unit (FPU)
        2. 2.3.3.2 Memory Protection Unit (MPU)
        3. 2.3.3.3 System Timer (SysTick)
        4. 2.3.3.4 Nested Vectored Interrupt Controller (NVIC)
        5. 2.3.3.5 System Control Block (SCB)
        6. 2.3.3.6 System Control Space (SCS)
        7. 2.3.3.7 Security Attribution Unit (SAU)
    4. 2.4 Programming Model
      1. 2.4.1 Modes of Operation and Execution
        1. 2.4.1.1 Security States
        2. 2.4.1.2 Operating Modes
        3. 2.4.1.3 Operating States
        4. 2.4.1.4 Privileged Access and Unprivileged User Access
      2. 2.4.2 Instruction Set Summary
      3. 2.4.3 Memory Model
        1. 2.4.3.1 Private Peripheral Bus
        2. 2.4.3.2 Unaligned Accesses
      4. 2.4.4 Exclusive Monitor
      5. 2.4.5 Processor Core Registers Summary
      6. 2.4.6 Exceptions
        1. 2.4.6.1 Exception Handling and Prioritization
      7. 2.4.7 Runtime Security
        1. 2.4.7.1 IDAU Watermark Registers
        2. 2.4.7.2 Secure Memory Range for Registers
        3. 2.4.7.3 Bus Topology
        4. 2.4.7.4 Intended Use
    5. 2.5 Arm® Cortex®-M33 Registers
      1. 2.5.1  CPU_ITM Registers
      2. 2.5.2  CPU_DWT Registers
      3. 2.5.3  CPU_SYSTICK Registers
      4. 2.5.4  CPU_NVIC Registers
      5. 2.5.5  CPU_SCS Registers
      6. 2.5.6  CPU_MPU Registers
      7. 2.5.7  CPU_SAU Registers
      8. 2.5.8  CPU_DCB Registers
      9. 2.5.9  CPU_SIG Registers
      10. 2.5.10 CPU_FPU Registers
      11. 2.5.11 CPU_TPIU Registers
  4. 3 Memory Map
    1. 3.1 Introduction
    2. 3.2 Memory Map (Secure and Non-secure)
      1. 3.2.1 Bus Security
    3. 3.3 Memory Map
  5. 4  Arm Cortex-M33 Peripherals
    1. 4.1 Arm Cortex-M33 Peripherals Introduction
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation and Hard Faults
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Fabric
      1. 5.4.1 Introduction
      2. 5.4.2 Event Fabric Overview
        1. 5.4.2.1 Registers
    5. 5.5 AON Event Fabric
      1. 5.5.1 Common Input Event List
      2. 5.5.2 Event Subscribers
        1. 5.5.2.1 AON Power Management Controller (AON_PMCTL)
        2. 5.5.2.2 Real-Time Clock
        3. 5.5.2.3 MCU Event Fabric
    6. 5.6 MCU Event Fabric
      1. 5.6.1 Common Input Event List
      2. 5.6.2 Event Subscribers
        1. 5.6.2.1 System CPU
        2. 5.6.2.2 NMI
        3. 5.6.2.3 Freeze
    7. 5.7 AON Events
    8. 5.8 Interrupts and Events Registers
      1. 5.8.1 AON_EVENT Registers
      2. 5.8.2 EVENT Registers
  7. 6 JTAG Interface
    1. 6.1 Overview
    2. 6.2 cJTAG
    3. 6.3 ICEPick
      1. 6.3.1 Secondary TAPs
        1. 6.3.1.1 Slave DAP (CPU DAP)
      2. 6.3.2 ICEPick Registers
        1. 6.3.2.1 IR Instructions
        2. 6.3.2.2 Data Shift Register
        3. 6.3.2.3 Instruction Register
        4. 6.3.2.4 Bypass Register
        5. 6.3.2.5 Device Identification Register
        6. 6.3.2.6 User Code Register
        7. 6.3.2.7 ICEPick Identification Register
        8. 6.3.2.8 Connect Register
      3. 6.3.3 Router Scan Chain
      4. 6.3.4 TAP Routing Registers
        1. 6.3.4.1 ICEPick Control Block
          1. 6.3.4.1.1 All0s Register
          2. 6.3.4.1.2 ICEPick Control Register
          3. 6.3.4.1.3 Linking Mode Register
        2. 6.3.4.2 Test TAP Linking Block
          1. 6.3.4.2.1 Secondary Test TAP Register
        3. 6.3.4.3 Debug TAP Linking Block
          1. 6.3.4.3.1 Secondary Debug TAP Register
    4. 6.4 ICEMelter
    5. 6.5 Serial Wire Viewer (SWV)
    6. 6.6 Halt In Boot (HIB)
    7. 6.7 Debug and Shutdown
    8. 6.8 Boundary Scan
  8. 7 Power, Reset, and Clock Management (PRCM)
    1. 7.1 Introduction
    2. 7.2 System CPU Mode
    3. 7.3 Supply System
      1. 7.3.1 Internal DC/DC Converter and Global LDO
      2. 7.3.2 External Regulator Mode
    4. 7.4 Digital Power Partitioning
      1. 7.4.1 MCU_VD
        1. 7.4.1.1 MCU_VD Power Domains
      2. 7.4.2 AON_VD
        1. 7.4.2.1 AON_VD Power Domains
    5. 7.5 Clock Management
      1. 7.5.1 System Clocks
        1. 7.5.1.1 Controlling the Oscillators
      2. 7.5.2 Clocks in MCU_VD
        1. 7.5.2.1 Clock Gating
        2. 7.5.2.2 Scaler to GPTs
        3. 7.5.2.3 Scaler to WDT
      3. 7.5.3 Clocks in AON_VD
    6. 7.6 Power Modes
      1. 7.6.1 Start-Up State
      2. 7.6.2 Active Mode
      3. 7.6.3 Idle Mode
      4. 7.6.4 Standby Mode
      5. 7.6.5 Shutdown Mode
    7. 7.7 Reset
      1. 7.7.1 System Resets
        1. 7.7.1.1 Clock Loss Detection
        2. 7.7.1.2 Software-Initiated System Reset
        3. 7.7.1.3 Warm Reset Converted to System Reset
      2. 7.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 7.7.3 Reset of AON_VD
      4. 7.7.4 Always On Watchdog Timer (AON_WDT)
    8. 7.8 PRCM Registers
      1. 7.8.1 PRCM Registers
      2. 7.8.2 AON_PMCTL Registers
      3. 7.8.3 DDI_0_OSC Registers
  9. 8 Versatile Instruction Memory System (VIMS)
    1. 8.1 Introduction
    2. 8.2 VIMS Configurations
      1. 8.2.1 VIMS Modes
        1. 8.2.1.1 GPRAM Mode
        2. 8.2.1.2 Off Mode
        3. 8.2.1.3 Cache Mode
      2. 8.2.2 VIMS FLASH Line Buffers
      3. 8.2.3 VIMS Arbitration
      4. 8.2.4 VIMS Cache TAG Prefetch
    3. 8.3 VIMS Software Remarks
      1. 8.3.1 FLASH Program or Update
      2. 8.3.2 VIMS Retention
        1. 8.3.2.1 Mode 1
        2. 8.3.2.2 Mode 2
        3. 8.3.2.3 Mode 3
    4. 8.4 FLASH
      1. 8.4.1 Flash Memory Protection
      2. 8.4.2 Flash Memory Programming
    5. 8.5 ROM Functions
    6. 8.6 VIMS Registers
      1. 8.6.1 FLASH Registers
      2. 8.6.2 VIMS Registers
      3. 8.6.3 NVMNW Registers
  10. 9 SRAM
    1. 9.1 Introduction
    2. 9.2 Main Features
    3. 9.3 Data Retention
    4. 9.4 Parity and SRAM Error Support
      1. 9.4.1 SRAM Extension Mode
    5. 9.5 SRAM Auto-Initialization
    6. 9.6 Parity Debug Behavior
    7. 9.7 SRAM Registers
      1. 9.7.1 SRAM_MMR Registers
      2. 9.7.2 SRAM Registers
  11. 10Bootloader
    1. 10.1 Bootloader Functionality
      1. 10.1.1 Bootloader Disabling
      2. 10.1.2 Bootloader Backdoor
    2. 10.2 Bootloader Interfaces
      1. 10.2.1 Packet Handling
        1. 10.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 10.2.2 Transport Layer
        1. 10.2.2.1 UART Transport
          1. 10.2.2.1.1 UART Baud Rate Automatic Detection
        2. 10.2.2.2 SPI Transport
      3. 10.2.3 Serial Bus Commands
        1. 10.2.3.1  COMMAND_PING
        2. 10.2.3.2  COMMAND_DOWNLOAD
        3. 10.2.3.3  COMMAND_GET_STATUS
        4. 10.2.3.4  COMMAND_SEND_DATA
        5. 10.2.3.5  COMMAND_RESET
        6. 10.2.3.6  COMMAND_SECTOR_ERASE
        7. 10.2.3.7  COMMAND_CRC32
        8. 10.2.3.8  COMMAND_GET_CHIP_ID
        9. 10.2.3.9  COMMAND_MEMORY_READ
        10. 10.2.3.10 COMMAND_MEMORY_WRITE
        11. 10.2.3.11 COMMAND_BANK_ERASE
        12. 10.2.3.12 COMMAND_SET_CCFG
        13. 10.2.3.13 COMMAND_DOWNLOAD_CRC
  12. 11Device Configuration
    1. 11.1 Customer Configuration (CCFG)
      1. 11.1.1 CCFG Recommendations for Final Production
    2. 11.2 CCFG Registers
    3. 11.3 Factory Configuration (FCFG)
    4. 11.4 FCFG1 Registers
  13. 12AES and Hash Cryptoprocessor
    1. 12.1 Introduction
    2. 12.2 Functional Description
      1. 12.2.1 Debug Capabilities
      2. 12.2.2 Exception Handling
      3. 12.2.3 Power Management and Sleep Modes
      4. 12.2.4 Interrupts
      5. 12.2.5 Module Memory Map
      6. 12.2.6 Master Control and Select Module
        1. 12.2.6.1 Algorithm Select Register
          1. 12.2.6.1.1 Algorithm Select
        2. 12.2.6.2 Master PROT Enable
          1. 12.2.6.2.1 Master PROT-Privileged Access-Enable
        3. 12.2.6.3 Software Reset
      7. 12.2.7 AES Engine
        1. 12.2.7.1 Second and Third Key Registers (Internal, but Clearable)
        2. 12.2.7.2 AES Initialization Vector (IV) Registers
        3. 12.2.7.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 12.2.7.4 AES Data Input and Output Registers
        5. 12.2.7.5 TAG Registers
      8. 12.2.8 Key Area Registers
        1. 12.2.8.1 Key Store Write Area Register
        2. 12.2.8.2 Key Store Written Area Register
        3. 12.2.8.3 Key Store Size Register
        4. 12.2.8.4 Key Store Read Area Register
      9. 12.2.9 Hash Engine
        1. 12.2.9.1 Hash I/O Buffer Control and Status Register, Mode, and Length Registers
        2. 12.2.9.2 Hash Data Input and Digest Registers
    3. 12.3 DMA Controller
      1. 12.3.1 Internal Operation
      2. 12.3.2 Supported DMA Operations
    4. 12.4 AES and Hash Cryptoprocessor Performance
      1. 12.4.1 Introduction
      2. 12.4.2 Performance for DMA-Based Operations
    5. 12.5 Programming Guidelines
      1. 12.5.1 One-Time Initialization After a Reset
      2. 12.5.2 DMAC and Master Control
        1. 12.5.2.1 Regular Use
        2. 12.5.2.2 Interrupting DMA Transfers
        3. 12.5.2.3 Interrupts, Hardware, and Software Synchronization
      3. 12.5.3 Hashing
        1. 12.5.3.1 Data Format and Byte Order
        2. 12.5.3.2 Basic Hash with Data From DMA
          1. 12.5.3.2.1 New Hash Session with Digest Read Through Slave
          2. 12.5.3.2.2 New Hash Session with Digest to External Memory
          3. 12.5.3.2.3 Resumed Hash Session
        3. 12.5.3.3 HMAC
          1. 12.5.3.3.1 Secure HMAC
        4. 12.5.3.4 Alternative Basic Hash Where Data Originates from Slave Interface
          1. 12.5.3.4.1 New Hash Session
          2. 12.5.3.4.2 Resumed Hash Session
      4. 12.5.4 Encryption and Decryption
        1. 12.5.4.1 Data Format and Byte Order
        2. 12.5.4.2 Key Store
          1. 12.5.4.2.1 Load Keys from External Memory
        3. 12.5.4.3 Basic AES Modes
          1. 12.5.4.3.1 AES-ECB
          2. 12.5.4.3.2 AES-CBC
          3. 12.5.4.3.3 AES-CTR
          4. 12.5.4.3.4 Programming Sequence with DMA Data
        4. 12.5.4.4 CBC-MAC
          1. 12.5.4.4.1 Programming Sequence for Regular CBC-MAC
          2. 12.5.4.4.2 Programming Sequence for Regular CBC-MAC with Continuation
          3. 12.5.4.4.3 Programming Sequence for CMAC CBC-MAC
          4. 12.5.4.4.4 Programming Sequence for CMAC CBC-MAC with Continuation
        5. 12.5.4.5 AES-CCM
          1. 12.5.4.5.1 Continued CCM Processing
          2. 12.5.4.5.2 Programming Sequence for AES-CCM
          3. 12.5.4.5.3 Programming Sequence for Continued AES-CCM in the AAD Phase
          4. 12.5.4.5.4 Programming Sequence for Continued AES-CCM in the Payload Phase
        6. 12.5.4.6 AES-GCM
          1. 12.5.4.6.1 Continued AES-GCM Processing
          2. 12.5.4.6.2 Programming Sequence for AES-GCM
          3. 12.5.4.6.3 Programming Sequence for Continued AES-GCM in the AAD Phase
          4. 12.5.4.6.4 Programming Sequence for Continued AES-GCM in the Payload Phase
      5. 12.5.5 Exceptions Handling
        1. 12.5.5.1 Soft Reset
        2. 12.5.5.2 External Port Errors
        3. 12.5.5.3 Key Store Errors
    6. 12.6 Conventions and Compliances
      1. 12.6.1 Conventions Used in This Manual
        1. 12.6.1.1 Terminology
        2. 12.6.1.2 Formulas and Nomenclature
      2. 12.6.2 Compliance
    7. 12.7 CRYPTO Registers
  14. 13PKA Engine
    1. 13.1 Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Module Architecture
      2. 13.2.2 PKA RAM
      3. 13.2.3 PKCP Operations
      4. 13.2.4 Sequencer Operations
        1. 13.2.4.1 Modular Exponentiation Operations
        2. 13.2.4.2 Modular Inversion Operation
        3. 13.2.4.3 ECC Operations
      5. 13.2.5 Operation Sequence
    3. 13.3 PKA Engine Performance
      1. 13.3.1 Basic Operations Performance
      2. 13.3.2 ExpMod Performance
      3. 13.3.3 Modular Inversion Performance
      4. 13.3.4 ECC Operation Performance
    4. 13.4 PKA Registers
  15. 14True Random Number Generator (TRNG)
    1. 14.1 Introduction
    2. 14.2 Block Diagram
    3. 14.3 TRNG Software Reset
    4. 14.4 Interrupt Requests
    5. 14.5 TRNG Operation Description
      1. 14.5.1 TRNG Shutdown
      2. 14.5.2 TRNG Alarms
      3. 14.5.3 TRNG Entropy
    6. 14.6 TRNG Low-Level Programming Guide
      1. 14.6.1 Initialization
        1. 14.6.1.1 Interfacing Modules
        2. 14.6.1.2 TRNG Main Sequence
        3. 14.6.1.3 TRNG Operating Modes
          1. 14.6.1.3.1 Polling Mode
          2. 14.6.1.3.2 Interrupt Mode
    7. 14.7 TRNG Registers
  16. 15I/O Controller (IOC)
    1. 15.1  Introduction
    2. 15.2  IOC Overview
    3. 15.3  I/O Mapping and Configuration
      1. 15.3.1 Basic I/O Mapping
      2. 15.3.2 Mapping AUXIOs to DIO Pins
      3. 15.3.3 Control External LNA/PA (Range Extender) with I/Os
      4. 15.3.4 Map the 32 kHz System Clock (SCLK_LF Clock) to DIO
    4. 15.4  Edge Detection on DIO Pins
      1. 15.4.1 Configure DIO as GPIO Input to Generate Interrupt on Edge Detect
    5. 15.5  Unused I/O Pins
    6. 15.6  GPIO
    7. 15.7  I/O Pin Capability
    8. 15.8  Peripheral PORT_IDs
    9. 15.9  I/O Pins
      1. 15.9.1 Input/Output Modes
        1. 15.9.1.1 Physical Pin
        2. 15.9.1.2 Pin Configuration
    10. 15.10 IOC Registers
      1. 15.10.1 AON_IOC Registers
      2. 15.10.2 GPIO Registers
      3. 15.10.3 IOC Registers
  17. 16Micro Direct Memory Access (µDMA)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1  Channel Assignments
      2. 16.3.2  Priority
      3. 16.3.3  Arbitration Size
      4. 16.3.4  Request Types
        1. 16.3.4.1 Single Request
        2. 16.3.4.2 Burst Request
      5. 16.3.5  Channel Configuration
      6. 16.3.6  Transfer Modes
        1. 16.3.6.1 Stop Mode
        2. 16.3.6.2 Basic Mode
        3. 16.3.6.3 Auto Mode
        4. 16.3.6.4 Ping-Pong Mode
        5. 16.3.6.5 Memory Scatter-Gather Mode
        6. 16.3.6.6 Peripheral Scatter-Gather Mode
      7. 16.3.7  Transfer Size and Increments
      8. 16.3.8  Peripheral Interface
      9. 16.3.9  Software Request
      10. 16.3.10 Interrupts and Errors
    4. 16.4 Initialization and Configuration
      1. 16.4.1 Module Initialization
      2. 16.4.2 Configuring a Memory-to-Memory Transfer
        1. 16.4.2.1 Configure the Channel Attributes
        2. 16.4.2.2 Configure the Channel Control Structure
        3. 16.4.2.3 Start the Transfer
    5. 16.5 UDMA Registers
  18. 17Timers
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 GPTM Reset Conditions
      2. 17.3.2 Timer Modes
        1. 17.3.2.1 One-Shot or Periodic Timer Mode
        2. 17.3.2.2 Input Edge-Count Mode
        3. 17.3.2.3 Input Edge-Time Mode
        4. 17.3.2.4 PWM Mode
        5. 17.3.2.5 Wait-for-Trigger Mode
      3. 17.3.3 Synchronizing GPT Blocks
      4. 17.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 17.4 Initialization and Configuration
      1. 17.4.1 One-Shot and Periodic Timer Modes
      2. 17.4.2 Input Edge-Count Mode
      3. 17.4.3 Input Edge-Timing Mode
      4. 17.4.4 PWM Mode
      5. 17.4.5 Producing DMA Trigger Events
    5. 17.5 GPT Registers
  19. 18Real-Time Clock (RTC)
    1. 18.1 Introduction
    2. 18.2 Functional Specifications
      1. 18.2.1 Functional Overview
      2. 18.2.2 Free-Running Counter
      3. 18.2.3 Channels
        1. 18.2.3.1 Capture and Compare
      4. 18.2.4 Events
    3. 18.3 RTC Register Information
      1. 18.3.1 Register Access
      2. 18.3.2 Entering Sleep and Wakeup From Sleep
      3. 18.3.3 AON_RTC:SYNC Register
    4. 18.4 RTC Registers
      1. 18.4.1 AON_RTC Registers
  20. 19Watchdog Timer (WDT)
    1. 19.1 Introduction
    2. 19.2 Functional Description
    3. 19.3 Initialization and Configuration
    4. 19.4 WDT Registers
  21. 20AUX Domain Sensor Controller and Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
        2. 20.2.2.2 Sensor Controller
      3. 20.2.3 SCE Clock Emulation
      4. 20.2.4 AUX RAM Retention
    3. 20.3 Sensor Controller
      1. 20.3.1 Sensor Controller Studio
        1. 20.3.1.1 Programming Model
        2. 20.3.1.2 Task Development
        3. 20.3.1.3 Task Testing, Task Debugging and Run-Time Logging
        4. 20.3.1.4 Documentation
      2. 20.3.2 Sensor Controller Engine (SCE)
        1. 20.3.2.1  Registers
          1.        Pipeline Hazards
        2. 20.3.2.2  Memory Architecture
          1.        Memory Access to Instructions and Data
          2.        I/O Access to Module Registers
        3. 20.3.2.3  Program Flow
          1.        Zero-Overhead Loop
        4. 20.3.2.4  Instruction Set
          1. 20.3.2.4.1 Instruction Timing
          2. 20.3.2.4.2 Instruction Prefix
          3. 20.3.2.4.3 Instructions
        5. 20.3.2.5  SCE Event Interface
        6. 20.3.2.6  Math Accelerator (MAC)
        7. 20.3.2.7  Programmable Microsecond Delay
        8. 20.3.2.8  Wake-Up Event Handling
        9. 20.3.2.9  Access to AON Domain Registers
        10. 20.3.2.10 VDDR Recharge
    4. 20.4 Digital Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 DDI Control-Configuration
      2. 20.4.2 Analog I/O Digital I/O (AIODIO)
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Mapping to DIO Pins
          2. 20.4.2.2.2 Configuration
          3. 20.4.2.2.3 GPIO Mode
          4. 20.4.2.2.4 Input Buffer
          5. 20.4.2.2.5 Data Output Source
      3. 20.4.3 Semaphore (SMPH)
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
        3. 20.4.3.3 Semaphore Allocation in TI Software
      4. 20.4.4 SPI Master (SPIM)
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 TX and RX Operations
          2. 20.4.4.2.2 Configuration
          3. 20.4.4.2.3 Timing Diagrams
      5. 20.4.5 Time-to-Digital Converter (TDC)
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Command
          2. 20.4.5.2.2 Conversion Time Configuration
          3. 20.4.5.2.3 Status and Result
          4. 20.4.5.2.4 Clock Source Selection
            1. 20.4.5.2.4.1 Counter Clock
            2. 20.4.5.2.4.2 Reference Clock
          5. 20.4.5.2.5 Start and Stop Events
          6. 20.4.5.2.6 Prescaler
        3. 20.4.5.3 Supported Measurement Types
          1. 20.4.5.3.1 Measure Pulse Width
          2. 20.4.5.3.2 Measure Frequency
          3. 20.4.5.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.4.5.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.4.5.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.4.5.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.4.5.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.4.5.3.4 Pulse Counting
      6. 20.4.6 Timer01
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
      7. 20.4.7 Timer2
        1. 20.4.7.1 Introduction
        2. 20.4.7.2 Functional Description
          1. 20.4.7.2.1 Clock Source
          2. 20.4.7.2.2 Clock Prescaler
          3. 20.4.7.2.3 Counter
          4. 20.4.7.2.4 Event Outputs
          5. 20.4.7.2.5 Channel Actions
            1. 20.4.7.2.5.1 Period and Pulse Width Measurement
            2. 20.4.7.2.5.2 Clear on Zero, Toggle on Compare Repeatedly
            3. 20.4.7.2.5.3 Set on Zero, Toggle on Compare Repeatedly
          6. 20.4.7.2.6 Asynchronous Bus Bridge
    5. 20.5 Analog Peripheral Modules
      1. 20.5.1 Overview
        1. 20.5.1.1 ADI Control-Configuration
        2. 20.5.1.2 Block Diagram
      2. 20.5.2 Analog-to-Digital Converter (ADC)
        1. 20.5.2.1 Introduction
        2. 20.5.2.2 Functional Description
          1. 20.5.2.2.1 Input Selection and Scaling
          2. 20.5.2.2.2 Reference Selection
          3. 20.5.2.2.3 ADC Sample Mode
          4. 20.5.2.2.4 ADC Clock Source
          5. 20.5.2.2.5 ADC Trigger
          6. 20.5.2.2.6 Sample FIFO
          7. 20.5.2.2.7 µDMA Interface
          8. 20.5.2.2.8 Resource Ownership and Usage
      3. 20.5.3 Comparator A (COMPA)
        1. 20.5.3.1 Introduction
        2. 20.5.3.2 Functional Description
          1. 20.5.3.2.1 Input Selection
          2. 20.5.3.2.2 Reference Selection
          3. 20.5.3.2.3 LPM Bias and COMPA Enable
          4. 20.5.3.2.4 Resource Ownership and Usage
      4. 20.5.4 Comparator B (COMPB)
        1. 20.5.4.1 Introduction
        2. 20.5.4.2 Functional Description
          1. 20.5.4.2.1 Input Selection
          2. 20.5.4.2.2 Reference Selection
          3. 20.5.4.2.3 Resource Ownership and Usage
            1. 20.5.4.2.3.1 Sensor Controller Wakeup
            2. 20.5.4.2.3.2 System CPU Wakeup
      5. 20.5.5 Reference Digital-to-Analog Converter (DAC)
        1. 20.5.5.1 Introduction
        2. 20.5.5.2 Functional Description
          1. 20.5.5.2.1 Reference Selection
          2. 20.5.5.2.2 Output Voltage Control and Range
          3. 20.5.5.2.3 Sample Clock
            1. 20.5.5.2.3.1 Automatic Phase Control
            2. 20.5.5.2.3.2 Manual Phase Control
            3. 20.5.5.2.3.3 Operational Mode Dependency
          4. 20.5.5.2.4 Output Selection
            1. 20.5.5.2.4.1 Buffer
            2. 20.5.5.2.4.2 External Load
            3. 20.5.5.2.4.3 COMPA_REF
            4. 20.5.5.2.4.4 COMPB_REF
          5. 20.5.5.2.5 LPM Bias
          6. 20.5.5.2.6 Resource Ownership and Usage
      6. 20.5.6 Current Source (ISRC)
        1. 20.5.6.1 Introduction
        2. 20.5.6.2 Functional Description
          1. 20.5.6.2.1 Programmable Current
          2. 20.5.6.2.2 Voltage Reference
          3. 20.5.6.2.3 ISRC Enable
          4. 20.5.6.2.4 Temperature Dependency
          5. 20.5.6.2.5 Resource Ownership and Usage
    6. 20.6 Event Routing and Usage
      1. 20.6.1 AUX Event Bus
        1. 20.6.1.1 Event Signals
        2. 20.6.1.2 Event Subscribers
          1. 20.6.1.2.1 Event Detection
            1. 20.6.1.2.1.1 Detection of Asynchronous Events
            2. 20.6.1.2.1.2 Detection of Synchronous Events
      2. 20.6.2 Event Observation on External Pin
      3. 20.6.3 Events From MCU Domain
      4. 20.6.4 Events to MCU Domain
      5. 20.6.5 Events From AON Domain
      6. 20.6.6 Events to AON Domain
      7. 20.6.7 µDMA Interface
    7. 20.7 Sensor Controller Alias Register Space
    8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
      1. 20.8.1  ADI_4_AUX Registers
      2. 20.8.2  AUX_AIODIO Registers
      3. 20.8.3  AUX_EVCTL Registers
      4. 20.8.4  AUX_SMPH Registers
      5. 20.8.5  AUX_TDC Registers
      6. 20.8.6  AUX_TIMER01 Registers
      7. 20.8.7  AUX_TIMER2 Registers
      8. 20.8.8  AUX_ANAIF Registers
      9. 20.8.9  AUX_SYSIF Registers
      10. 20.8.10 AUX_SPIM Registers
      11. 20.8.11 AUX_MAC Registers
      12. 20.8.12 AUX_SCE Registers
  22. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 AON_BATMON Registers
  23. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud Rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to µDMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
  24. 23Serial Peripheral Interface (SPI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
          1. 23.4.2.1.1 Repeated Transmit Operation
        2. 23.4.2.2 Receive FIFO
        3. 23.4.2.3 FIFO Flush
      3. 23.4.3 Interrupts
      4. 23.4.4 Data Format
      5. 23.4.5 Delayed Data Sampling
      6. 23.4.6 Frame Formats
        1. 23.4.6.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.6.2 Motorola SPI Frame Format
          1. 23.4.6.2.1 SPO Clock Polarity Bit
          2. 23.4.6.2.2 SPH Phase Control Bit
        3. 23.4.6.3 Motorola SPI Frame Format with SPO = 0 and SPH = 0
        4. 23.4.6.4 Motorola SPI Frame Format with SPO = 0 and SPH = 1
        5. 23.4.6.5 Motorola SPI Frame Format with SPO = 1 and SPH = 0
        6. 23.4.6.6 Motorola SPI Frame Format with SPO = 1 and SPH = 1
        7. 23.4.6.7 MICROWIRE Frame Format
    5. 23.5 μDMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SPI Registers
  25. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format with 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
  26. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
  27. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization with Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command with Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond with Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          19. 26.3.3.2.19 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry from Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries from Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® Low Energy
      1. 26.6.1 Bluetooth® Low Energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® Low Energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® Low Energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Non-connectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
  28. 27Revision History

11.4 FCFG1 Registers

Table 11-33 lists the memory-mapped registers for the FCFG1 registers. All register offset addresses not listed in Table 11-33 should be considered as reserved locations and the register contents should not be modified.

Table 11-33 FCFG1 Registers
OffsetAcronymRegister NameSection
A0hMISC_CONF_1Misc configurationsSection 11.4.1
A4hMISC_CONF_2InternalSection 11.4.2
B0hHPOSC_MEAS_5InternalSection 11.4.3
B4hHPOSC_MEAS_4InternalSection 11.4.4
B8hHPOSC_MEAS_3InternalSection 11.4.5
BChHPOSC_MEAS_2InternalSection 11.4.6
C0hHPOSC_MEAS_1InternalSection 11.4.7
C4hCONFIG_CC26_FEInternalSection 11.4.8
C8hCONFIG_CC13_FEInternalSection 11.4.9
CChCONFIG_RF_COMMONInternalSection 11.4.10
D0hCONFIG_SYNTH_DIV2_CC26_2G4InternalSection 11.4.11
D4hCONFIG_SYNTH_DIV2_CC13_2G4InternalSection 11.4.12
D8hCONFIG_SYNTH_DIV2_CC26_1GInternalSection 11.4.13
DChCONFIG_SYNTH_DIV2_CC13_1GInternalSection 11.4.14
E0hCONFIG_SYNTH_DIV4_CC26InternalSection 11.4.15
E4hCONFIG_SYNTH_DIV4_CC13InternalSection 11.4.16
E8hCONFIG_SYNTH_DIV5InternalSection 11.4.17
EChCONFIG_SYNTH_DIV6_CC26InternalSection 11.4.18
F0hCONFIG_SYNTH_DIV6_CC13InternalSection 11.4.19
F4hCONFIG_SYNTH_DIV10InternalSection 11.4.20
F8hCONFIG_SYNTH_DIV12_CC26InternalSection 11.4.21
FChCONFIG_SYNTH_DIV12_CC13InternalSection 11.4.22
100hCONFIG_SYNTH_DIV15InternalSection 11.4.23
104hCONFIG_SYNTH_DIV30InternalSection 11.4.24
144hIOCONFIO ConfigurationSection 11.4.25
294hUSER_IDUser Identification.Section 11.4.26
2B0hFLASH_OTP_DATA3InternalSection 11.4.27
2B4hANA2_TRIMInternalSection 11.4.28
2B8hLDO_TRIMInternalSection 11.4.29
2E8hMAC_BLE_0MAC BLE Address 0Section 11.4.30
2EChMAC_BLE_1MAC BLE Address 1Section 11.4.31
2F0hMAC_15_4_0MAC IEEE 802.15.4 Address 0Section 11.4.32
2F4hMAC_15_4_1MAC IEEE 802.15.4 Address 1Section 11.4.33
30ChMISC_TRIMMiscellaneous Trim ParametersSection 11.4.34
310hRCOSC_HF_TEMPCOMPInternalSection 11.4.35
318hICEPICK_DEVICE_IDIcePick Device IdentificationSection 11.4.36
31ChFCFG1_REVISIONFactory Configuration (FCFG1) RevisionSection 11.4.37
320hMISC_OTP_DATAMisc OTP DataSection 11.4.38
34ChCONFIG_IF_ADCInternalSection 11.4.39
350hCONFIG_OSC_TOPInternalSection 11.4.40
35ChSOC_ADC_ABS_GAINAUX_ADC Gain in Absolute Reference ModeSection 11.4.41
360hSOC_ADC_REL_GAINAUX_ADC Gain in Relative Reference ModeSection 11.4.42
368hSOC_ADC_OFFSET_INTAUX_ADC Temperature Offsets in Absolute Reference ModeSection 11.4.43
36ChSOC_ADC_REF_TRIM_AND_OFFSET_EXTInternalSection 11.4.44
370hAMPCOMP_TH1InternalSection 11.4.45
374hAMPCOMP_TH2InternalSection 11.4.46
378hAMPCOMP_CTRL1InternalSection 11.4.47
37ChANABYPASS_VALUE2InternalSection 11.4.48
388hVOLT_TRIMInternalSection 11.4.49
38ChOSC_CONFOSC ConfigurationSection 11.4.50
390hFREQ_OFFSETInternalSection 11.4.51
398hMISC_OTP_DATA_1InternalSection 11.4.52
3D0hSHDW_DIE_ID_0Shadow of EFUSE:DIE_ID_0 registerSection 11.4.53
3D4hSHDW_DIE_ID_1Shadow of EFUSE:DIE_ID_1 registerSection 11.4.54
3D8hSHDW_DIE_ID_2Shadow of EFUSE:DIE_ID_2 registerSection 11.4.55
3DChSHDW_DIE_ID_3Shadow of EFUSE:DIE_ID_3 registerSection 11.4.56
3F8hSHDW_SCAN_MCU3_SECInternalSection 11.4.57
3FChSHDW_SCAN_DATA1_CRCInternalSection 11.4.58
404hSHDW_ANA_TRIMInternalSection 11.4.59
408hOSC_CONF1Oscillator configurationSection 11.4.60
40ChDAC_BIAS_CNFInternalSection 11.4.61
418hTFW_PROBEInternalSection 11.4.62
41ChTFW_FTInternalSection 11.4.63
420hDAC_CAL0InternalSection 11.4.64
424hDAC_CAL1InternalSection 11.4.65
428hDAC_CAL2InternalSection 11.4.66
42ChDAC_CAL3InternalSection 11.4.67

Complex bit access types are encoded to fit into small table cells. Table 11-34 shows the codes that are used for access types in this section.

Table 11-34 FCFG1 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

11.4.1 MISC_CONF_1 Register (Offset = A0h) [Reset = FFFFFF00h]

MISC_CONF_1 is shown in Table 11-35.

Return to the Summary Table.

Misc configurations

Table 11-35 MISC_CONF_1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0DEVICE_MINOR_REVRXHW minor revision number (a value of 0xFF shall be treated equally to 0x00).
Any test of this field by SW should be implemented as a 'greater or equal' comparison as signed integer.
Value may change without warning.

Default value holds log information from production test.

11.4.2 MISC_CONF_2 Register (Offset = A4h) [Reset = FFFFFF00h]

MISC_CONF_2 is shown in Table 11-36.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-36 MISC_CONF_2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0HPOSC_COMP_P3RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11.4.3 HPOSC_MEAS_5 Register (Offset = B0h) [Reset = 00000000h]

HPOSC_MEAS_5 is shown in Table 11-37.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-37 HPOSC_MEAS_5 Register Field Descriptions
BitFieldTypeResetDescription
31-16HPOSC_D5RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

15-8HPOSC_T5RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

7-0HPOSC_DT5RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

11.4.4 HPOSC_MEAS_4 Register (Offset = B4h) [Reset = 00000000h]

HPOSC_MEAS_4 is shown in Table 11-38.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-38 HPOSC_MEAS_4 Register Field Descriptions
BitFieldTypeResetDescription
31-16HPOSC_D4RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

15-8HPOSC_T4RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

7-0HPOSC_DT4RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

11.4.5 HPOSC_MEAS_3 Register (Offset = B8h) [Reset = 00000000h]

HPOSC_MEAS_3 is shown in Table 11-39.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-39 HPOSC_MEAS_3 Register Field Descriptions
BitFieldTypeResetDescription
31-16HPOSC_D3RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

15-8HPOSC_T3RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

7-0HPOSC_DT3RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

11.4.6 HPOSC_MEAS_2 Register (Offset = BCh) [Reset = 00000000h]

HPOSC_MEAS_2 is shown in Table 11-40.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-40 HPOSC_MEAS_2 Register Field Descriptions
BitFieldTypeResetDescription
31-16HPOSC_D2RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

15-8HPOSC_T2RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

7-0HPOSC_DT2RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

11.4.7 HPOSC_MEAS_1 Register (Offset = C0h) [Reset = 00000000h]

HPOSC_MEAS_1 is shown in Table 11-41.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-41 HPOSC_MEAS_1 Register Field Descriptions
BitFieldTypeResetDescription
31-16HPOSC_D1RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

15-8HPOSC_T1RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

7-0HPOSC_DT1RXInternal. Only to be used through TI provided API.

Default value holds log information from production test.

11.4.8 CONFIG_CC26_FE Register (Offset = C4h) [Reset = 70000F00h]

CONFIG_CC26_FE is shown in Table 11-42.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-42 CONFIG_CC26_FE Register Field Descriptions
BitFieldTypeResetDescription
31-28IFAMP_IBR7hInternal. Only to be used through TI provided API.
27-24LNA_IBRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

23-19IFAMP_TRIMR0hInternal. Only to be used through TI provided API.
18-14CTL_PA0_TRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

13PATRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12RSSITRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-8RESERVEDR0hReserved
7-0RSSI_OFFSETRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11.4.9 CONFIG_CC13_FE Register (Offset = C8h) [Reset = 70000F00h]

CONFIG_CC13_FE is shown in Table 11-43.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-43 CONFIG_CC13_FE Register Field Descriptions
BitFieldTypeResetDescription
31-28IFAMP_IBR7hInternal. Only to be used through TI provided API.
27-24LNA_IBRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

23-19IFAMP_TRIMR0hInternal. Only to be used through TI provided API.
18-14CTL_PA0_TRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

13PATRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

12RSSITRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-8RESERVEDR0hReserved
7-0RSSI_OFFSETRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11.4.10 CONFIG_RF_COMMON Register (Offset = CCh) [Reset = 81C0014Dh]

CONFIG_RF_COMMON is shown in Table 11-44.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-44 CONFIG_RF_COMMON Register Field Descriptions
Bit Field Type Reset Description
31 DISABLE_CORNER_CAP R 1h Internal. Only to be used through TI provided API.
30-25 SLDO_TRIM_OUTPUT R X Internal. Only to be used through TI provided API.

Default value holds trim value from production test.
24-22 RESERVED R 0h Reserved
21 PA20DBMTRIMCOMPLETE_N R X Internal. Only to be used through TI provided API.
20-16 CTL_PA_20DBM_TRIM R X Internal. Only to be used through TI provided API.

Default value holds trim value from production test.
15-9 RFLDO_TRIM_OUTPUT R X Internal. Only to be used through TI provided API.
8-6 QUANTCTLTHRES R 5h Internal. Only to be used through TI provided API.
5-0 DACTRIM R Dh Internal. Only to be used through TI provided API.

11.4.11 CONFIG_SYNTH_DIV2_CC26_2G4 Register (Offset = D0h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV2_CC26_2G4 is shown in Table 11-45.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-45 CONFIG_SYNTH_DIV2_CC26_2G4 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

11.4.12 CONFIG_SYNTH_DIV2_CC13_2G4 Register (Offset = D4h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV2_CC13_2G4 is shown in Table 11-46.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-46 CONFIG_SYNTH_DIV2_CC13_2G4 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

11.4.13 CONFIG_SYNTH_DIV2_CC26_1G Register (Offset = D8h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV2_CC26_1G is shown in Table 11-47.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-47 CONFIG_SYNTH_DIV2_CC26_1G Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

11.4.14 CONFIG_SYNTH_DIV2_CC13_1G Register (Offset = DCh) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV2_CC13_1G is shown in Table 11-48.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-48 CONFIG_SYNTH_DIV2_CC13_1G Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

11.4.15 CONFIG_SYNTH_DIV4_CC26 Register (Offset = E0h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV4_CC26 is shown in Table 11-49.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-49 CONFIG_SYNTH_DIV4_CC26 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

11.4.16 CONFIG_SYNTH_DIV4_CC13 Register (Offset = E4h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV4_CC13 is shown in Table 11-50.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-50 CONFIG_SYNTH_DIV4_CC13 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

11.4.17 CONFIG_SYNTH_DIV5 Register (Offset = E8h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV5 is shown in Table 11-51.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-51 CONFIG_SYNTH_DIV5 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

11.4.18 CONFIG_SYNTH_DIV6_CC26 Register (Offset = ECh) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV6_CC26 is shown in Table 11-52.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-52 CONFIG_SYNTH_DIV6_CC26 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

11.4.19 CONFIG_SYNTH_DIV6_CC13 Register (Offset = F0h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV6_CC13 is shown in Table 11-53.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-53 CONFIG_SYNTH_DIV6_CC13 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

11.4.20 CONFIG_SYNTH_DIV10 Register (Offset = F4h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV10 is shown in Table 11-54.

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Internal. Only to be used through TI provided API.

Table 11-54 CONFIG_SYNTH_DIV10 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

11.4.21 CONFIG_SYNTH_DIV12_CC26 Register (Offset = F8h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV12_CC26 is shown in Table 11-55.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-55 CONFIG_SYNTH_DIV12_CC26 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

11.4.22 CONFIG_SYNTH_DIV12_CC13 Register (Offset = FCh) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV12_CC13 is shown in Table 11-56.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-56 CONFIG_SYNTH_DIV12_CC13 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

11.4.23 CONFIG_SYNTH_DIV15 Register (Offset = 100h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV15 is shown in Table 11-57.

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Internal. Only to be used through TI provided API.

Table 11-57 CONFIG_SYNTH_DIV15 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

11.4.24 CONFIG_SYNTH_DIV30 Register (Offset = 104h) [Reset = 0000001Fh]

CONFIG_SYNTH_DIV30 is shown in Table 11-58.

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Internal. Only to be used through TI provided API.

Table 11-58 CONFIG_SYNTH_DIV30 Register Field Descriptions
BitFieldTypeResetDescription
31-28MIN_ALLOWED_RTRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-12RFC_MDM_DEMIQMC0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-6LDOVCO_TRIM_OUTPUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

5RFC_MDM_DEMIQMC0_TRIMCOMPLETE_NRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

4-0RESERVEDR0hReserved

11.4.25 IOCONF Register (Offset = 144h) [Reset = FFFFFF00h]

IOCONF is shown in Table 11-59.

Return to the Summary Table.

IO Configuration

Table 11-59 IOCONF Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0GPIO_CNTRXNumber of available DIOs.

Default value differs depending on partnumber.

11.4.26 USER_ID Register (Offset = 294h) [Reset = 10000000h]

USER_ID is shown in Table 11-60.

Return to the Summary Table.

User Identification.
Reading this register and the FCFG1:ICEPICK_DEVICE_ID register is the only supported way of identifying a device.
The value of this register will be written to AON_PMCTL:JTAGUSERCODE by boot FW while in safezone.

Table 11-60 USER_ID Register Field Descriptions
BitFieldTypeResetDescription
31-28PG_REVR1hField used to distinguish revisions of the device
27-26VERRXVersion number.
0x0: Bits [25:12] of this register has the stated meaning.
Any other setting indicate a different encoding of these bits.

Default value differs depending on partnumber.

25PARX0: Does not support 20dBm PA
1: Supports 20dBM PA

Default value differs depending on partnumber.

24RESERVEDR0hReserved
23CC13RX0: CC26x4x10 device type
1: CC13x4x10 device type

Default value differs depending on partnumber.

22-19SEQUENCERXSequence.
Used to differentiate between marketing/orderable product where other fields of this register are the same (temp range, flash size, voltage range etc)

Default value differs depending on partnumber.

18-16PKGRXPackage type.
0x2: 7x7mm QFN (RGZ) package
0x7: 8x8mm QFN (RSK) package
Other values are reserved for future use.
Packages available for a specific device are shown in the device datasheet.

Default value differs depending on partnumber.

15-12PROTOCOLRXProtocols supported.
0x1: BLE
0x2: RF4CE
0x4: Zigbee/6lowpan
0x8: Proprietary
More than one protocol can be supported on same device - values above are then combined.

Default value differs depending on partnumber.

11-0RESERVEDR0hReserved

11.4.27 FLASH_OTP_DATA3 Register (Offset = 2B0h) [Reset = FFFFFFF8h]

FLASH_OTP_DATA3 is shown in Table 11-61.

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Internal. Only to be used through TI provided API.

Table 11-61 FLASH_OTP_DATA3 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0FLASH_SIZERXInternal. Only to be used through TI provided API.

Default value differs depending on partnumber.

11.4.28 ANA2_TRIM Register (Offset = 2B4h) [Reset = 8240087Fh]

ANA2_TRIM is shown in Table 11-62.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-62 ANA2_TRIM Register Field Descriptions
BitFieldTypeResetDescription
31RCOSCHFCTRIMFRACT_ENR1hInternal. Only to be used through TI provided API.
30-26RCOSCHFCTRIMFRACTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

25RESERVEDR0hReserved
24-23

SET_RCOSC_HF_FINE_

RESISTOR

RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

22

ATESTLF_UDIGLDO_

IBIAS_TRIM

R1hInternal. Only to be used through TI provided API.
21-15NANOAMP_RES_TRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

14-12DCDC_DRV_DSRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11DITHER_ENR1hInternal. Only to be used through TI provided API.
10-8DCDC_IPEAKR0hInternal. Only to be used through TI provided API.
7-6DEAD_TIME_TRIMR1hInternal. Only to be used through TI provided API.
5-3DCDC_LOW_EN_SELR7hInternal. Only to be used through TI provided API.
2-0DCDC_HIGH_EN_SELR7hInternal. Only to be used through TI provided API.

11.4.29 LDO_TRIM Register (Offset = 2B8h) [Reset = E0F8E0FBh]

LDO_TRIM is shown in Table 11-63.

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Internal. Only to be used through TI provided API.

Table 11-63 LDO_TRIM Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-24VDDR_TRIM_SLEEPRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

23-19RESERVEDR0hReserved
18-16GLDO_CURSRCR0hInternal. Only to be used through TI provided API.
15-13RESERVEDR0hReserved
12-11ITRIM_DIGLDO_LOADR0hInternal. Only to be used through TI provided API.
10-8ITRIM_UDIGLDOR0hInternal. Only to be used through TI provided API.
7-3RESERVEDR0hReserved
2-0VTRIM_DELTAR3hInternal. Only to be used through TI provided API.

11.4.30 MAC_BLE_0 Register (Offset = 2E8h) [Reset = 00000000h]

MAC_BLE_0 is shown in Table 11-64.

Return to the Summary Table.

MAC BLE Address 0

Table 11-64 MAC_BLE_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDR_0_31RXThe first 32-bits of the 64-bit MAC BLE address

Default value holds trim value from production test.

11.4.31 MAC_BLE_1 Register (Offset = 2ECh) [Reset = 00000000h]

MAC_BLE_1 is shown in Table 11-65.

Return to the Summary Table.

MAC BLE Address 1

Table 11-65 MAC_BLE_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDR_32_63RXThe last 32-bits of the 64-bit MAC BLE address

Default value holds trim value from production test.

11.4.32 MAC_15_4_0 Register (Offset = 2F0h) [Reset = 00000000h]

MAC_15_4_0 is shown in Table 11-66.

Return to the Summary Table.

MAC IEEE 802.15.4 Address 0

Table 11-66 MAC_15_4_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDR_0_31RXThe first 32-bits of the 64-bit MAC 15.4 address

Default value holds trim value from production test.

11.4.33 MAC_15_4_1 Register (Offset = 2F4h) [Reset = 00000000h]

MAC_15_4_1 is shown in Table 11-67.

Return to the Summary Table.

MAC IEEE 802.15.4 Address 1

Table 11-67 MAC_15_4_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDR_32_63RXThe last 32-bits of the 64-bit MAC 15.4 address

Default value holds trim value from production test.

11.4.34 MISC_TRIM Register (Offset = 30Ch) [Reset = FFFE003Bh]

MISC_TRIM is shown in Table 11-68.

Return to the Summary Table.

Miscellaneous Trim Parameters

Table 11-68 MISC_TRIM Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16-12

TRIM_RECHARGE_

COMP_OFFSET

RXInternal. Only to be used through TI provided API.
11-8

TRIM_RECHARGE_

COMP_REFLEVEL

RXInternal. Only to be used through TI provided API.
7-0TEMPVSLOPER3BhSigned byte value representing the TEMP slope with battery voltage, in degrees C / V, with four fractional bits.

11.4.35 RCOSC_HF_TEMPCOMP Register (Offset = 310h) [Reset = 00000003h]

RCOSC_HF_TEMPCOMP is shown in Table 11-69.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-69 RCOSC_HF_TEMPCOMP Register Field Descriptions
BitFieldTypeResetDescription
31-24FINE_RESISTORR0hInternal. Only to be used through TI provided API.
23-16CTRIMR0hInternal. Only to be used through TI provided API.
15-8CTRIMFRACT_QUADR0hInternal. Only to be used through TI provided API.
7-0CTRIMFRACT_SLOPER3hInternal. Only to be used through TI provided API.

11.4.36 ICEPICK_DEVICE_ID Register (Offset = 318h) [Reset = 1BB7802Fh]

ICEPICK_DEVICE_ID is shown in Table 11-70.

Return to the Summary Table.

IcePick Device Identification
Reading this register and the FCFG1:USER_ID register is the only supported way of identifying a device.

Table 11-70 ICEPICK_DEVICE_ID Register Field Descriptions
BitFieldTypeResetDescription
31-28PG_REVR1hField used to distinguish revisions of the device.
27-12WAFER_IDRBB78hField used to identify silicon die.
11-0MANUFACTURER_IDR2FhManufacturer code.
0x02F: Texas Instruments

11.4.37 FCFG1_REVISION Register (Offset = 31Ch) [Reset = 0000002Ah]

FCFG1_REVISION is shown in Table 11-71.

Return to the Summary Table.

Factory Configuration (FCFG1) Revision

Table 11-71 FCFG1_REVISION Register Field Descriptions
BitFieldTypeResetDescription
31-0REVR2AhThe revision number of the FCFG1 layout. This value will be read by application SW in order to determine which FCFG1 parameters that have valid values. This revision number must be incremented by 1 before any devices are to be produced if the FCFG1 layout has changed since the previous production of devices.
Value migth change without warning.

11.4.38 MISC_OTP_DATA Register (Offset = 320h) [Reset = 0000CFFFh]

MISC_OTP_DATA is shown in Table 11-72.

Return to the Summary Table.

Misc OTP Data

Table 11-72 MISC_OTP_DATA Register Field Descriptions
BitFieldTypeResetDescription
31-28RCOSC_HF_ITUNERXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

27-20RCOSC_HF_CRIMRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

19-15PER_MR1hInternal. Only to be used through TI provided API.
14-12PER_ER4hInternal. Only to be used through TI provided API.
11-0RESERVEDR0hReserved

11.4.39 CONFIG_IF_ADC Register (Offset = 34Ch) [Reset = 3460F400h]

CONFIG_IF_ADC is shown in Table 11-73.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-73 CONFIG_IF_ADC Register Field Descriptions
Bit Field Type Reset Description
31-28 FF2ADJ R 3h Internal. Only to be used through TI provided API.
27-24 FF3ADJ R 4h Internal. Only to be used through TI provided API.
23-20 INT3ADJ R 6h Internal. Only to be used through TI provided API.
19-16 FF1ADJ R 0h Internal. Only to be used through TI provided API.
15-14 AAFCAP R 3h Internal. Only to be used through TI provided API.
13-10 INT2ADJ R Dh Internal. Only to be used through TI provided API.
9-5 IFDIGLDO_TRIM_OUTPUT R X Internal. Only to be used through TI provided API.

Default value holds trim value from production test.
4-0 IFANALDO_TRIM_OUTPUT R X Internal. Only to be used through TI provided API.

Default value holds trim value from production test.

11.4.40 CONFIG_OSC_TOP Register (Offset = 350h) [Reset = DC07FC00h]

CONFIG_OSC_TOP is shown in Table 11-74.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-74 CONFIG_OSC_TOP Register Field Descriptions
Bit Field Type Reset Description
31-30 RESERVED R 0h Reserved
29-26 XOSC_HF_ROW_Q12 R 7h Internal. Only to be used through TI provided API.
25-10 XOSC_HF_COLUMN_Q12 R 1FFh Internal. Only to be used through TI provided API.
9-2 RCOSCLF_CTUNE_TRIM R X Internal. Only to be used through TI provided API.

Default value holds trim value from production test.
1-0 RCOSCLF_RTUNE_TRIM R 0h Internal. Only to be used through TI provided API.

11.4.41 SOC_ADC_ABS_GAIN Register (Offset = 35Ch) [Reset = 00000000h]

SOC_ADC_ABS_GAIN is shown in Table 11-75.

Return to the Summary Table.

AUX_ADC Gain in Absolute Reference Mode

Table 11-75 SOC_ADC_ABS_GAIN Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 SOC_ADC_ABS_GAIN_TEMP1 R X SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated in production test..

Default value holds log information from production test.

11.4.42 SOC_ADC_REL_GAIN Register (Offset = 360h) [Reset = 00000000h]

SOC_ADC_REL_GAIN is shown in Table 11-76.

Return to the Summary Table.

AUX_ADC Gain in Relative Reference Mode

Table 11-76 SOC_ADC_REL_GAIN Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 SOC_ADC_REL_GAIN_TEMP1 R X SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated in production test..

Default value holds trim value from production test.

11.4.43 SOC_ADC_OFFSET_INT Register (Offset = 368h) [Reset = 00000000h]

SOC_ADC_OFFSET_INT is shown in Table 11-77.

Return to the Summary Table.

AUX_ADC Temperature Offsets in Absolute Reference Mode

Table 11-77 SOC_ADC_OFFSET_INT Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16

SOC_ADC_REL_

OFFSET_TEMP1

RXSOC_ADC offset in relative reference mode at temperature 1 (30C). Signed 8-bit number. Calculated in production test..

Default value holds trim value from production test.

15-8RESERVEDR0hReserved
7-0

SOC_ADC_ABS_

OFFSET_TEMP1

RXSOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed 8-bit number. Calculated in production test..

Default value holds trim value from production test.

11.4.44 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register (Offset = 36Ch) [Reset = 0000C080h]

SOC_ADC_REF_TRIM_AND_OFFSET_EXT is shown in Table 11-78.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-78 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h Reserved
5-0 SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 R X Internal. Only to be used through TI provided API.

Default value holds trim value from production test.

11.4.45 AMPCOMP_TH1 Register (Offset = 370h) [Reset = FF7B828Eh]

AMPCOMP_TH1 is shown in Table 11-79.

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Internal. Only to be used through TI provided API.

Table 11-79 AMPCOMP_TH1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-18HPMRAMP3_LTHR1EhInternal. Only to be used through TI provided API.
17-16RESERVEDR0hReserved
15-10HPMRAMP3_HTHR20hInternal. Only to be used through TI provided API.
9-6

IBIASCAP_LPTOHP_

OL_CNT

RAhInternal. Only to be used through TI provided API.
5-0HPMRAMP1_THREhInternal. Only to be used through TI provided API.

11.4.46 AMPCOMP_TH2 Register (Offset = 374h) [Reset = 6B8B0303h]

AMPCOMP_TH2 is shown in Table 11-80.

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Internal. Only to be used through TI provided API.

Table 11-80 AMPCOMP_TH2 Register Field Descriptions
Bit Field Type Reset Description
31-26 LPMUPDATE_LTH R 1Ah Internal. Only to be used through TI provided API.
25-24 RESERVED R 0h Reserved
23-18 LPMUPDATE_HTM R 22h Internal. Only to be used through TI provided API.
17-16 RESERVED R 0h Reserved
15-10 ADC_COMP_AMPTH_LPM R 0h Internal. Only to be used through TI provided API.
9-8 RESERVED R 0h Reserved
7-2 ADC_COMP_AMPTH_HPM R 0h Internal. Only to be used through TI provided API.
1-0 RESERVED R 0h Reserved

11.4.47 AMPCOMP_CTRL1 Register (Offset = 378h) [Reset = FF483F47h]

AMPCOMP_CTRL1 is shown in Table 11-81.

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Internal. Only to be used through TI provided API.

Table 11-81 AMPCOMP_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30AMPCOMP_REQ_MODER1hInternal. Only to be used through TI provided API.
29-24RESERVEDR0hReserved
23-20IBIAS_OFFSETR4hInternal. Only to be used through TI provided API.
19-16IBIAS_INITR8hInternal. Only to be used through TI provided API.
15-8

LPM_IBIAS_WAIT_

CNT_FINAL

R3FhInternal. Only to be used through TI provided API.
7-4CAP_STEPR4hInternal. Only to be used through TI provided API.
3-0

IBIASCAP_HPTOLP_

OL_CNT

R7hInternal. Only to be used through TI provided API.

11.4.48 ANABYPASS_VALUE2 Register (Offset = 37Ch) [Reset = FFFFC3FFh]

ANABYPASS_VALUE2 is shown in Table 11-82.

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Internal. Only to be used through TI provided API.

Table 11-82 ANABYPASS_VALUE2 Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-0XOSC_HF_IBIASTHERMR3FFhInternal. Only to be used through TI provided API.

11.4.49 VOLT_TRIM Register (Offset = 388h) [Reset = E0E0E0E0h]

VOLT_TRIM is shown in Table 11-83.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-83 VOLT_TRIM Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-24VDDR_TRIM_HHRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

23-21RESERVEDR0hReserved
20-16VDDR_TRIM_HRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-13RESERVEDR0hReserved
12-8VDDR_TRIM_SLEEP_HRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

7-5RESERVEDR0hReserved
4-0TRIMBOD_HRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11.4.50 OSC_CONF Register (Offset = 38Ch) [Reset = F00900E6h]

OSC_CONF is shown in Table 11-84.

Return to the Summary Table.

OSC Configuration

Table 11-84 OSC_CONF Register Field Descriptions
Bit Field Type Reset Description
31-30 RESERVED R 0h Reserved
29 ADC_SH_VBUF_EN R 1h Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN.
28 ADC_SH_MODE_EN R 1h Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN.
27

ATESTLF_RCOSCLF_

IBIAS_TRIM

 R 0h Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM.
26-25

XOSCLF_REGULATOR_

TRIM

 R 0h Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM.
24-21

XOSCLF_CMIRRWR_

RATIO

 R 0h Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO.
20-19 XOSC_HF_FAST_START R 1h Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START.
18 XOSC_OPTION R X 0: XOSC_HF unavailable (may not be bonded out)
1: XOSC_HF available (default)

Default value differs depending on partnumber.
17 HPOSC_OPTION R X Internal. Only to be used through TI provided API.

Default value differs depending on partnumber.
16

HPOSC_BIAS_HOLD_

MODE_EN

 R 1h Internal. Only to be used through TI provided API.
15-12

HPOSC_CURRMIRR_

RATIO

 R X Internal. Only to be used through TI provided API.

Default value holds trim value from production test.
11-8 HPOSC_BIAS_RES_SET R X Internal. Only to be used through TI provided API.

Default value holds trim value from production test.
7 HPOSC_FILTER_EN R 1h Internal. Only to be used through TI provided API.
6-5

HPOSC_BIAS_RECHARGE

_DELAY

 R 3h Internal. Only to be used through TI provided API.
4-3 RESERVED R 0h Reserved
2-1 HPOSC_SERIES_CAP R 3h Internal. Only to be used through TI provided API.
0 HPOSC_DIV3_BYPASS R 0h Internal. Only to be used through TI provided API.

11.4.51 FREQ_OFFSET Register (Offset = 390h) [Reset = 00000000h]

FREQ_OFFSET is shown in Table 11-85.

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Internal. Only to be used through TI provided API.

Table 11-85 FREQ_OFFSET Register Field Descriptions
BitFieldTypeResetDescription
31-16HPOSC_COMP_P0RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-8HPOSC_COMP_P1RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

7-0HPOSC_COMP_P2RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11.4.52 MISC_OTP_DATA_1 Register (Offset = 398h) [Reset = E08403F8h]

MISC_OTP_DATA_1 is shown in Table 11-86.

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Internal. Only to be used through TI provided API.

Table 11-86 MISC_OTP_DATA_1 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-27PEAK_DET_ITRIMR0hInternal. Only to be used through TI provided API.
26-24HP_BUF_ITRIMR0hInternal. Only to be used through TI provided API.
23-22LP_BUF_ITRIMR2hInternal. Only to be used through TI provided API.
21-20

DBLR_LOOP_FILTER_

RESET_VOLTAGE

R0hInternal. Only to be used through TI provided API.
19-10HPM_IBIAS_WAIT_CNTR100hInternal. Only to be used through TI provided API.
9-4LPM_IBIAS_WAIT_CNTR3FhInternal. Only to be used through TI provided API.
3-0IDAC_STEPR8hInternal. Only to be used through TI provided API.

11.4.53 SHDW_DIE_ID_0 Register (Offset = 3D0h) [Reset = 00000000h]

SHDW_DIE_ID_0 is shown in Table 11-87.

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Shadow of DIE_ID_0 register in eFuse

Table 11-87 SHDW_DIE_ID_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0ID_31_0RXShadow of DIE_ID_0 register in eFuse row number 5

Default value depends on eFuse value.

11.4.54 SHDW_DIE_ID_1 Register (Offset = 3D4h) [Reset = 00000000h]

SHDW_DIE_ID_1 is shown in Table 11-88.

Return to the Summary Table.

Shadow of DIE_ID_1 register in eFuse

Table 11-88 SHDW_DIE_ID_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0ID_63_32RXShadow of DIE_ID_1 register in eFuse row number 6

Default value depends on eFuse value.

11.4.55 SHDW_DIE_ID_2 Register (Offset = 3D8h) [Reset = 00000000h]

SHDW_DIE_ID_2 is shown in Table 11-89.

Return to the Summary Table.

Shadow of DIE_ID_2 register in eFuse

Table 11-89 SHDW_DIE_ID_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0ID_95_64RXShadow of DIE_ID_2 register in eFuse row number 7

Default value depends on eFuse value.

11.4.56 SHDW_DIE_ID_3 Register (Offset = 3DCh) [Reset = 00000000h]

SHDW_DIE_ID_3 is shown in Table 11-90.

Return to the Summary Table.

Shadow of DIE_ID_3 register in eFuse

Table 11-90 SHDW_DIE_ID_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0ID_127_96RXShadow of DIE_ID_3 register in eFuse row number 8

Default value depends on eFuse value.

11.4.57 SHDW_SCAN_MCU3_SEC Register (Offset = 3F8h) [Reset = 00000000h]

SHDW_SCAN_MCU3_SEC is shown in Table 11-91.

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Internal. Only to be used through TI provided API.

Table 11-91 SHDW_SCAN_MCU3_SEC Register Field Descriptions
Bit Field Type Reset Description
31-24 SECURITY R X Internal. Only to be used through TI provided API.

Default value depends on eFuse value.
23 RESERVED R 0h Reserved
22-11 ULL_MCU_RAM_0_REP R X Internal. Only to be used through TI provided API.

Default value depends on eFuse value.
10-0 ULL_MCU_RAM_1_REP_1 R X Internal. Only to be used through TI provided API.

Default value depends on eFuse value.

11.4.58 SHDW_SCAN_DATA1_CRC Register (Offset = 3FCh) [Reset = 00000000h]

SHDW_SCAN_DATA1_CRC is shown in Table 11-92.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-92 SHDW_SCAN_DATA1_CRC Register Field Descriptions
BitFieldTypeResetDescription
31FLASH_RDYRXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

30-9RESERVEDR0hReserved
8-1CRCRXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

0TAP_DAP_LOCK_NRXInternal. Only to be used through TI provided API.

Default value depends on eFuse value.

11.4.59 SHDW_ANA_TRIM Register (Offset = 404h) [Reset = 00000000h]

SHDW_ANA_TRIM is shown in Table 11-93.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-93 SHDW_ANA_TRIM Register Field Descriptions
Bit Field Type Reset Description
31 RESERVED R 0h Reserved
30 ALT_VDDR_TRIM R X Internal. Only to be used through TI provided API.

Default value depends on eFuse value.
29 DET_LOGIC_DIS R X Internal. Only to be used through TI provided API.

Default value depends on eFuse value.
28-27 BOD_BANDGAP_TRIM_CNF_EXT R X Internal. Only to be used through TI provided API.

Default value depends on eFuse value.
26-25 BOD_BANDGAP_TRIM_CNF R X Internal. Only to be used through TI provided API.

Default value depends on eFuse value.
24 VDDR_ENABLE_PG1 R X Internal. Only to be used through TI provided API.

Default value depends on eFuse value.
23 VDDR_OK_HYS R X Internal. Only to be used through TI provided API.

Default value depends on eFuse value.
22-21 IPTAT_TRIM R X Internal. Only to be used through TI provided API.

Default value depends on eFuse value.
20-16 VDDR_TRIM R X Internal. Only to be used through TI provided API.

Default value depends on eFuse value.
15-11 TRIMBOD_INTMODE R X Internal. Only to be used through TI provided API.

Default value depends on eFuse value.
10-6 TRIMBOD_EXTMODE R X Internal. Only to be used through TI provided API.

Default value depends on eFuse value.
5-0 TRIMTEMP R X Internal. Only to be used through TI provided API.

Default value depends on eFuse value.

11.4.60 OSC_CONF1 Register (Offset = 408h) [Reset = 03FF0000h]

OSC_CONF1 is shown in Table 11-94.

Return to the Summary Table.

Oscillator configuration

Table 11-94 OSC_CONF1 Register Field Descriptions
Bit Field Type Reset Description
31-28

RCOSC_MF_BIAS_

HTEMP

 R X Defines the MF_BIAS trim code to use for high temp.
Only valid if RCOSC_MF_SINGLE_TRIM_METHOD == 0

Default value holds trim value from production test.
27

RCOSC_MF_TEMP_

DEPEND_MODE

 R X Defines whether dual trim was needed:
0: Dual trims needed on this chip
1: Dual trims not needed on this chip

Default value holds trim value from production test.
26

RCOSC_MF_SINGLE_

TRIM_METHOD

 R X Defines trim method used:
0: Dual trim method
1: Single trim method

Default value holds trim value from production test.
25-4 RESERVED R 0h Reserved
3-0 RCOSC_MF_BIAS_ADJ R X Value is written to DDI_0_OSC:RCOSCMFCTL.RCOSC_MF_BIAS_ADJ by boot FW while in safezone.

Default value holds trim value from production test.

11.4.61 DAC_BIAS_CNF Register (Offset = 40Ch) [Reset = FFFC00FFh]

DAC_BIAS_CNF is shown in Table 11-95.

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Internal. Only to be used through TI provided API.

Table 11-95 DAC_BIAS_CNF Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17-12LPM_TRIM_IOUTRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11-9LPM_BIAS_WIDTH_TRIMR0hInternal. Only to be used through TI provided API.
8LPM_BIAS_BACKUP_ENR0hInternal. Only to be used through TI provided API.
7-0RESERVEDR0hReserved

11.4.62 TFW_PROBE Register (Offset = 418h) [Reset = 00000000h]

TFW_PROBE is shown in Table 11-96.

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Internal. Only to be used through TI provided API.

Table 11-96 TFW_PROBE Register Field Descriptions
BitFieldTypeResetDescription
31-0REVRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11.4.63 TFW_FT Register (Offset = 41Ch) [Reset = 00000000h]

TFW_FT is shown in Table 11-97.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-97 TFW_FT Register Field Descriptions
BitFieldTypeResetDescription
31-0REVRXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11.4.64 DAC_CAL0 Register (Offset = 420h) [Reset = 00000000h]

DAC_CAL0 is shown in Table 11-98.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-98 DAC_CAL0 Register Field Descriptions
BitFieldTypeResetDescription
31-16

SOC_DAC_VOUT_CAL_

DECOUPLE_C2

RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-0

SOC_DAC_VOUT_CAL_

DECOUPLE_C1

RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11.4.65 DAC_CAL1 Register (Offset = 424h) [Reset = 00000000h]

DAC_CAL1 is shown in Table 11-99.

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Internal. Only to be used through TI provided API.

Table 11-99 DAC_CAL1 Register Field Descriptions
BitFieldTypeResetDescription
31-16

SOC_DAC_VOUT_CAL_

PRECH_C2

RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-0

SOC_DAC_VOUT_CAL_

PRECH_C1

RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11.4.66 DAC_CAL2 Register (Offset = 428h) [Reset = 00000000h]

DAC_CAL2 is shown in Table 11-100.

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Internal. Only to be used through TI provided API.

Table 11-100 DAC_CAL2 Register Field Descriptions
BitFieldTypeResetDescription
31-16

SOC_DAC_VOUT_CAL_

ADCREF_C2

RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-0

SOC_DAC_VOUT_CAL_

ADCREF_C1

RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

11.4.67 DAC_CAL3 Register (Offset = 42Ch) [Reset = 00000000h]

DAC_CAL3 is shown in Table 11-101.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 11-101 DAC_CAL3 Register Field Descriptions
BitFieldTypeResetDescription
31-16

SOC_DAC_VOUT_CAL_

VDDS_C2

RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.

15-0

SOC_DAC_VOUT_CAL_

VDDS_C1

RXInternal. Only to be used through TI provided API.

Default value holds trim value from production test.