SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Bit | Field | Width | Type | Reset | Description |
---|---|---|---|---|---|
23–8 | Reserved | 16 | R/W | 0 | Reserved |
7 | KeepPoweredinTLR | 1 | R/W | 0 | When 1, the JTAG power domain stays on even in the Test Logic Reset (TLR) state. When 0, the JTAG power domain will be powered down in the Test Logic Reset (TLR) state if ICEPick is visible and TMS is 1. |
6 | BlockSysReset | 1 | R/W | 0 | When 1, the device system reset signal is blocked. |
5–1 | Reserved | 5 | R/W | 0 | Reserved |
0 | SystemReset | 1 | R/W | 0 | Debug probe controlled System Reset |