SLVUCM5 july   2023 TPS6521905 , TPS6521905-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4Programming Instructions
    1. 4.1  Configuring Enable Settings
    2. 4.2  Configuring the Bucks
    3. 4.3  Configuring LDOs
    4. 4.4  Configuring GPIOs
    5. 4.5  Configuring Sequence
    6. 4.6  Configuring Multi-Function Pins
    7. 4.7  Configuring the EN/PB/VSENSE Pin
    8. 4.8  Changing I2C Address
    9. 4.9  Configuring Mask Settings
    10. 4.10 NVM Re-Programming
  8.   A Non-NVM Registers
  9.   B Loading a NVM Configuration File to PMIC
  10.   C PMIC Configurable Fields
  11.   D References

4.6 Configuring Multi-Function Pins

The TPS65219 PMIC has three configurable multi-function pins. MODE/STBY and MODE/RESET can be configured as MODE to select the switching, as STBY to trigger a transition to Standby state, or as RESET to trigger a cold or warm reset. The VSEL_SD/VSEL_DDR pin can be configured to set the output voltage on LDO1 or LDO2 (selectable) or to set the output voltage on Buck3. Refer to the data sheet for information on pin polarity.

Note: If VSEL_SD/VSEL_DDR is not used to set the output voltage on LDO1 (or LDO2), then it must be configured as DDR and pulled to GND with a pull-down resistor in the schematic. Additionally, VSEL_SD_I2C_CTRL must be programmed to 1h.

  • Figure 4-7 shows the settings to be changed when using the TPS65219-GUI

  • Figure 4-7 show the register fields to be written when NOT using the TPS65219-GUI.

GUID-20230428-SS0I-MQDQ-HFRC-2V24NMCZKDPC-low.svg Figure 4-7 Multi-Function Configuration using the TPS65219-GUI
Table 4-16 NVM Registers for VSEL_SD / VSEL_DDR
Register Address Bit Settings
Bit # Field Name
Pin Function 0x1F 0 VSEL_DDR_SD 0h = VSEL pin configured as DDR to set the voltage on Buck3

1h = VSEL pin configured as SD to set the voltage on the VSEL_RAIL
VSEL rail selection 2 VSEL_RAIL 0h = LDO1

1h = LDO2

Pin polarity 1 VSEL_SD_POLARITY 0h =

  • LOW: 1.8V
  • HIGH: LDOx_VOUT register

1h =

  • HIGH: 1.8V
  • LOW: LDOx_VOUT register
Table 4-17 NVM Registers for MODE / STBY
Register Address Bit Settings
Bit # Field Name
Pin Function 0x20 1-0 MODE_STBY_CONFIG 0h = MODE

1h = STBY

2h = MODE and STBY

3h = MODE
Pin Polarity 0x1F 4 MODE_STBY_POLARITY see register map on data sheet
Table 4-18 NVM Registers for MODE / RESET
Register Address Bit Settings
Bit # Field Name
Pin Function 0x20 2 MODE_RESET_CONFIG 0h = MODE

1h = RESET
RESET config 6 WARM_COLD_RESET_CONFIG 0h = COLD RESET

1h = WARM RESET

Pin Polarity 0x1F 5 MODE_RESET_POLARITY see register map on data sheet