SLVUCM5 july   2023 TPS6521905 , TPS6521905-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4Programming Instructions
    1. 4.1  Configuring Enable Settings
    2. 4.2  Configuring the Bucks
    3. 4.3  Configuring LDOs
    4. 4.4  Configuring GPIOs
    5. 4.5  Configuring Sequence
    6. 4.6  Configuring Multi-Function Pins
    7. 4.7  Configuring the EN/PB/VSENSE Pin
    8. 4.8  Changing I2C Address
    9. 4.9  Configuring Mask Settings
    10. 4.10 NVM Re-Programming
  8.   A Non-NVM Registers
  9.   B Loading a NVM Configuration File to PMIC
  10.   C PMIC Configurable Fields
  11.   D References

4.5 Configuring Sequence

The process to configure the PMIC sequence consist of the following two steps:

  1. Power-up/Power-down slot assignment: The slot assignment defines the order in which rails turn ON or OFF. Each of the PMIC rails must have a slot assigned. There are 16 slots available (0-15). Multiple rails (including GPIOs) can be assigned to the same slot so they be enabled at the same time.
  2. Power-up/Power-down slot duration: The slot duration is the timing between the start of one slot to the start of the next slot. For example, if Buck1 is assigned to slot0 with a 3ms duration and Buck2 is assigned to slot 1, then Buck2 turns ON 3ms after Buck1.

Note: The slot duration does not dictate how long it takes for the rails to ramp. The slot duration only specifies how long the PMIC waits before enabling (or disabling) the rails that were assigned to the next slot.

  • Figure 4-6 shows the settings to be changed when using the TPS65219-GUI

GUID-20230505-SS0I-JK9B-QDLL-LWFZHG1GCBF4-low.svg Figure 4-6 Sequence Configuration
Table 4-12 Power-Up Sequence - Slot Assignments
Register Address Bit Settings
Bit# Field Name
Power-up Sequence

Slot Assignment

 0x11 7-4 BUCK1_SEQUENCE_ON_SLOT see register map on data sheet
0x10 7-4 BUCK2_SEQUENCE_ON_SLOT see register map on data sheet
0xF 7-4 BUCK3_SEQUENCE_ON_SLOT see register map on data sheet
0xE 7-4 LDO1_SEQUENCE_ON_SLOT see register map on data sheet
0xD 7-4 LDO2_SEQUENCE_ON_SLOT see register map on data sheet
0xC 7-4 LDO3_SEQUENCE_ON_SLOT see register map on data sheet
0xB 7-4 LDO4_SEQUENCE_ON_SLOT see register map on data sheet
0x15 7-4 GPO1_SEQUENCE_ON_SLOT see register map on data sheet
0x14 7-4 GPO2_SEQUENCE_ON_SLOT see register map on data sheet
0x13 7-4 GPIO_SEQUENCE_ON_SLOT see register map on data sheet
0x12 7-4 nRST_SEQUENCE_ON_SLOT see register map on data sheet
Table 4-13 Power-Up Sequence - Slot Duration
Register Address Bit Settings
Bit# Field Name
Power-up Sequence

Slot Duration

 0x16 7-6 POWER_UP_SLOT_0_DURATION see register map on data sheet
5-4 POWER_UP_SLOT_1_DURATION see register map on data sheet
3-2 POWER_UP_SLOT_2_DURATION see register map on data sheet
1-0 POWER_UP_SLOT_3_DURATION see register map on data sheet
0x17 7-6 POWER_UP_SLOT_4_DURATION see register map on data sheet
5-4 POWER_UP_SLOT_5_DURATION see register map on data sheet
3-2 POWER_UP_SLOT_6_DURATION see register map on data sheet
1-0 POWER_UP_SLOT_7_DURATION see register map on data sheet
0x18 7-6 POWER_UP_SLOT_8_DURATION see register map on data sheet
5-4 POWER_UP_SLOT_9_DURATION see register map on data sheet
3-2 POWER_UP_SLOT_10_DURATION see register map on data sheet
1-0 POWER_UP_SLOT_11_DURATION see register map on data sheet
0x19 7-6 POWER_UP_SLOT_12_DURATION see register map on data sheet
5-4 POWER_UP_SLOT_13_DURATION see register map on data sheet
3-2 POWER_UP_SLOT_14_DURATION see register map on data sheet
1-0 POWER_UP_SLOT_15_DURATION see register map on data sheet
Table 4-14 Power-Down Sequence - Slot Assignments
Register Address Bit Settings
Bit# Field Name
Power-down Sequence

Slot Assignment

 0x11 7-4 BUCK1_SEQUENCE_OFF_SLOT see register map on data sheet
0x10 7-4 BUCK2_SEQUENCE_OFF_SLOT see register map on data sheet
0xF 7-4 BUCK3_SEQUENCE_OFF_SLOT see register map on data sheet
0xE 7-4 LDO1_SEQUENCE_OFF_SLOT see register map on data sheet
0xD 7-4 LDO2_SEQUENCE_OFF_SLOT see register map on data sheet
0xC 7-4 LDO3_SEQUENCE_OFF_SLOT see register map on data sheet
0xB 7-4 LDO4_SEQUENCE_OFF_SLOT see register map on data sheet
0x15 7-4 GPO1_SEQUENCE_OFF_SLOT see register map on data sheet
0x14 7-4 GPO2_SEQUENCE_OFF_SLOT see register map on data sheet
0x13 7-4 GPIO_SEQUENCE_OFF_SLOT see register map on data sheet
0x12 7-4 nRST_SEQUENCE_OFF_SLOT see register map on data sheet
Table 4-15 Power-Down Sequence - Slot Duration
Register Address Bit Settings
Bit# Field Name
Power-down Sequence

Slot Duration

 0x1A 7-6 POWER_DOWN_SLOT_0_DURATION see register map on data sheet
5-4 POWER_DOWN_SLOT_1_DURATION see register map on data sheet
3-2 POWER_DOWN_SLOT_2_DURATION see register map on data sheet
1-0 POWER_DOWN_SLOT_3_DURATION see register map on data sheet
0x1B 7-6 POWER_DOWN_SLOT_4_DURATION see register map on data sheet
5-4 POWER_DOWN_SLOT_5_DURATION see register map on data sheet
3-2 POWER_DOWN_SLOT_6_DURATION see register map on data sheet
1-0 POWER_DOWN_SLOT_7_DURATION see register map on data sheet
0x1C 7-6 POWER_DOWN_SLOT_8_DURATION see register map on data sheet
5-4 POWER_DOWN_SLOT_9_DURATION see register map on data sheet
3-2 POWER_DOWN_SLOT_10_DURATION see register map on data sheet
1-0 POWER_DOWN_SLOT_11_DURATION see register map on data sheet
0x1D 7-6 POWER_DOWN_SLOT_12_DURATION see register map on data sheet
5-4 POWER_DOWN_SLOT_13_DURATION see register map on data sheet
3-2 POWER_DOWN_SLOT_14_DURATION see register map on data sheet
1-0 POWER_DOWN_SLOT_15_DURATION see register map on data sheet