SLVUCM5 july   2023 TPS6521905 , TPS6521905-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4Programming Instructions
    1. 4.1  Configuring Enable Settings
    2. 4.2  Configuring the Bucks
    3. 4.3  Configuring LDOs
    4. 4.4  Configuring GPIOs
    5. 4.5  Configuring Sequence
    6. 4.6  Configuring Multi-Function Pins
    7. 4.7  Configuring the EN/PB/VSENSE Pin
    8. 4.8  Changing I2C Address
    9. 4.9  Configuring Mask Settings
    10. 4.10 NVM Re-Programming
  8.   A Non-NVM Registers
  9.   B Loading a NVM Configuration File to PMIC
  10.   C PMIC Configurable Fields
  11.   D References

4.3 Configuring LDOs

There are several settings that can be programmed for the LDO regulators. These include the output voltages, and under voltage (UV) monitoring among others.

  • Figure 4-4 shows the settings to be changed when using the TPS65219-GUI.

GUID-20230428-SS0I-10MF-3HHF-QJV1CHTLQ69B-low.svg Figure 4-4 LDOs Settings Using the TPS65219-GUI
Table 4-6 NVM Registers for LDO1 Settings
Register Address Bit Settings
Bit # Field Name
Output Voltage 0x07 5-0 LDO1_VSET see register map on data sheet
Configuration 7 LDO1_LSW_CONFIG 0h = LDO1 NOT configured as load-switch

1h = LDO1 configured as Load-switch
6 LDO1_BYP_CONFIG 0h = LDO1 configured as LDO

1h = LDO1 configured as Bypass

(only applicable if LDO1_LSW_CONFIG 0x0)
UV monitoring 0x1E 3 LDO1_UV_THR 0h = -5% UV

1h = -10% UV

Table 4-7 NVM Registers for LDO2 Settings
Register Address Bit Settings
Bit # Field Name
Output Voltage 0x06 7 LDO2_VSET see register map on data sheet
Configuration 6 LDO2_LSW_CONFIG 0h = LDO1 NOT configured as load-switch

1h = LDO1 configured as Load-switch
5-0 LDO2_BYP_CONFIG 0h = LDO1 configured as LDO

1h = LDO1 configured as Bypass

(only applicable if LDO1_LSW_CONFIG 0x0)
UV Monitoring 0x1E 4 LDO2_UV_THR 0h = -5% UV

1h = -10% UV

Table 4-8 NVM Registers for LDO3 Settings
Register Address Bit Settings
Bit # Field Name
Output Voltage 0x05 5-0 LDO3_VSET see register map on data sheet
Configuration 6 LDO3_LSW_CONFIG 0h = LDO Mode

1h = LSW Mode

Ramp 7 LDO3_SLOW_PU_RAMP 0h = Fast ramp for power-up

1h = Slow ramp for power-up
UV Monitoring 0x1E 5 LDO3_UV_THR 0h = -5% UV

1h = -10% UV

Table 4-9 NVM Registers for LDO4 Settings
Register Address Bit Settings
Bit # Field Name
Output Voltage 0x04 5-0 LDO4_VSET see register map on data sheet
Configuration 6 LDO4_LSW_CONFIG 0h = LDO Mode

1h = LSW Mode

Ramp 7 LDO4_SLOW_PU_RAMP 0h = Fast ramp for power-up

1h = Slow ramp for power-up
UV Monitoring 0x1E 6 LDO4_UV_THR 0h = -5% UV

1h = -10% UV