What limits power density: thermal performance

A key factor that plays into overall power density is the thermal performance of the system. The better the package is at getting heat out, the more power losses you can typically afford without seeing unreasonable temperature rises. These factors are typically captured in data-sheet parameters such as the junction-to-ambient thermal resistance (R_ӨJA), along with careful estimates of application conditions. For more details on common thermal impedance values in MOSFET data sheets, watch the video: Understanding MOSFET data sheets: Thermal Impedances.

The overall goal of the thermal optimization of a package and printed circuit board (PCB) is to reduce the temperature rise in the presence of the power converter losses. As the trends toward miniaturization and cost reduction have progressed, the overall size of the converter, power switch and gate driver solution has shrunk. This has caused system-level thermal designs to become increasingly difficult because smaller silicon and package sizes typically result in worse thermal performance, as indicated in Figure 6. As the die area shrinks, the associated junction-to-ambient thermal resistance (R_ӨJA) gets exponentially worse.

What this graph clearly shows is that as package size, die size and overall power density improve, the expected thermal performance degrades rapidly unless you prioritize innovations in package thermal performance (dissipating the heat) and reducing power losses (generating less heat).