SNAA393 January   2024 LMK6H

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Why use a Phase Noise Analyzer?
  5. 2Understanding Phase Noise Plots
  6. 3Phase Noise Analyzer Measurement Settings
    1. 3.1 Start or Stop Frequency
    2. 3.2 Averaging and Correlation
    3. 3.3 Persistence
    4. 3.4 Spurious View Modes
    5. 3.5 Other Settings
  7. 4Hardware Setup for Different Clocking Formats
    1. 4.1 LVCMOS
    2. 4.2 LVDS
    3. 4.3 LVPECL/HCSL
    4. 4.4 Balun Recommendations
  8. 5Typical Measurements with Different Termination Schemes
    1. 5.1 LVCMOS
    2. 5.2 LVDS
    3. 5.3 LVPECL
    4. 5.4 HCSL
  9. 6Summary
  10. 7References

Why use a Phase Noise Analyzer?

Measuring time-domain jitter characteristics, such as total jitter (TJ) and cycle-to-cycle jitter, can be done using a high speed oscilloscope as described in the How to Measure Total Jitter (TJ) application note. However, for many applications time-domain jitter measurements are not as relevant compared to their frequency-domain counterparts such as integrated jitter or phase noise. For example, in wired networking applications the RMS jitter integrated from 12kHz to 20MHz is commonly used to make sure that the bit-error rate (BER) of an Ethernet PHY meets system-level requirements. As another example, medical imaging equipment can have strict phase noise requirements at a specific offset close to the carrier frequency (such as a 1kHz offset). For these types of applications, use a phase noise analyzer (PNA) due to the low noise floor and advanced jitter calculation tools. Oscilloscopes, spectrum analyzers, and other equipment are not recommended to measure phase noise for high performance clocks due to their high noise floor. Some PNAs that TI uses for device characterization include the Agilent E5052, R&S FSWP, and Microchip 53100A.