SNAA393 January   2024 LMK6H

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Why use a Phase Noise Analyzer?
  5. 2Understanding Phase Noise Plots
  6. 3Phase Noise Analyzer Measurement Settings
    1. 3.1 Start or Stop Frequency
    2. 3.2 Averaging and Correlation
    3. 3.3 Persistence
    4. 3.4 Spurious View Modes
    5. 3.5 Other Settings
  7. 4Hardware Setup for Different Clocking Formats
    1. 4.1 LVCMOS
    2. 4.2 LVDS
    3. 4.3 LVPECL/HCSL
    4. 4.4 Balun Recommendations
  8. 5Typical Measurements with Different Termination Schemes
    1. 5.1 LVCMOS
    2. 5.2 LVDS
    3. 5.3 LVPECL
    4. 5.4 HCSL
  9. 6Summary
  10. 7References

2 Understanding Phase Noise Plots

GUID-20231201-SS0I-BVRP-H6B0-P61RMFHRNZTC-low.svg Figure 2-1 Phase Noise Curve

A phase noise plot shows the noise of a clock source in the frequency-domain.

The Y-axis shows the power of noise in units of dBc/Hz - Decibels relative to the carrier signal with a bandwidth of 1Hz.

The X-axis is the offset from the carrier frequency in Hz.

Integrating a region of the phase noise curve can give the RMS jitter in units of seconds according to the following equation:

Equation 1. R M S   J i t t e r = 2 × 10 N 10 2 × π × f  

where N is the integral of the phase noise curve over a specified integration band (usually 12kHz - 20MHz) and f is the carrier frequency in Hz.