SPRAD05B May 2023 – December 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
It is recommended to indicate the configured boot mode in the block diagram. This includes the primary boot and the backup boot.
The processor family includes multiple peripheral interfaces that support boot mode. Examples include: eMMC, Multi-Media Card/Secure Digital (MMC/SD), QSPI, OSPI, GPMC NAND, GPMC NOR, Ethernet, USB (Device and Host), Serial Flash, xSPI and Inter-Integrated Circuit (I2C). The processor family supports a primary boot mode option and an optional backup boot mode option. If the primary boot source fails to boot, the ROM moves on to the backup mode.
The boot mode resistor configurations connected to the processor boot mode input pins provide information on the boot mode to be used by the ROM code during boot. The boot mode pins are sampled at power-on-reset (PORz_OUT), and the inputs must be stable before releasing (deassertion) the reset (MCU_PORz).
Boot mode configurations provide the below information:
PLL Config: BOOTMODE [02:00] – Indicates the system clock (PLL reference clock selection) frequency (MCU_OSC0_XI/XO) to ROM code for PLL configuration
Primary Boot Mode: BOOTMODE [06:03] – Select the required boot (primary) mode after POR, that is, the peripheral/memory to boot from
Primary Boot Mode Config: BOOTMODE [09:07] – These pins provide optional configurations for primary boot and are used in conjunction with the boot mode selected
Backup Boot Mode: BOOTMODE [12:10] – Select the required backup boot mode. This is the peripheral/memory to boot from, in case primary boot fails
Backup Boot Mode Config: BOOTMODE [13] – This pin provides additional configuration options (optional - depends on the selected backup boot mode) for the backup boot devices
Reserved: BOOTMODE [15:14] – Reserved pins
Key considerations for boot mode configuration:
For details regarding supported boot modes, refer the Initialization chapter of the device-specific TRM.