SPRAD05B May 2023 – December 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The processor includes three external reset input pins (MCU Domain cold reset (MCU_PORz), MCU Domain warm reset (MCU_RESETz) and Main Domain warm reset request (RESET_REQz)). Note the errata related to MCU_RESETz and MCU_RESETSTATz.
Be sure to make the recommended connections in the Pin Connectivity Requirements section of the device-specific data sheet.
The reset methods supported by the processor are described in detail in the device-specific data sheet and TRM.
The processor provides three reset status output pins (MCU Domain warm reset status (MCU_RESETSTATz), Main Domain POR (cold reset) status (PORz_OUT) and Main Domain warm reset status (RESETSTATz)). Note the errata related to MCU_RESETz and MCU_RESETSTATz.
Use of Reset status outputs are application dependent. Reset status outputs when not used can be left unconnected. It is recommended to provision for a test point for testing or future enhancements.
3.3 V inputs can be applied to MCU_PORz (3.3 V tolerant, fail-safe input). The input thresholds are a function of the 1.8 V IO supply voltage (VDDS_OSC0).
It is recommended to hold the MCU_PORz low during the supply ramp-up and crystal/oscillator start-up. Follow the recommended MCU_PORz timing requirement in the Power-Up Sequencing diagram of the device-specific data sheet.
Additional reset modes are available through processor internal registers and emulation.