CD4081B CMOS Quad 2-Input AND Gate | TI.com

CD4081B (ACTIVE)

CMOS Quad 2-Input AND Gate

CMOS Quad 2-Input AND Gate - CD4081B
Datasheet
 

Description

CD4073B, CD4081B and CD4082B AND gates, provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates.

The CD4073B, CD4081B, and CD4082B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

Features

  • Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range: 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

CD4073B Triple 3-Input AND Gate
CD4081B Quad 2-Input AND Gate
CD4082B Dual 4-Input AND Gate
Data sheet acquired from Harris Semiconductor

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Parametrics Compare all products in AND gate

 
Technology Family
VCC (Min) (V)
VCC (Max) (V)
Channels (#)
Inputs per channel
ICC @ nom voltage (Max) (mA)
IOL (Max) (mA)
IOH (Max) (mA)
Input type
Output type
Features
Data rate (Max) (Mbps)
Rating
Operating temperature range (C)
Package Group
Package size: mm2:W x L (PKG)
CD4081B
CD4000    
3    
18    
4    
2    
0.015    
6.8    
-6.8    
Standard CMOS    
Push-Pull    
High Speed (tpd 10-50ns)    
8    
Catalog    
-55 to 125    
PDIP | 14
SOIC | 14
SO | 14
TSSOP | 14    
See datasheet (PDIP)
14SO: 80 mm2: 7.8 x 10.2 (SO | 14)
14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)
14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)