The SMJ320C80 is a single-chip, MIMD parallel processor capable of performing over two billion operations per second. It consists of a 32-bit RISC master processor with a 100-MFLOPS (million floating-point operations per second) IEEE floating-point unit, four 32-bit parallel processing digital signal processors (DSPs), a transfer controller with up to 400-MBps off-chip transfer rate, and a video controller. All the processors are coupled tightly through an on-chip crossbar that provides shared access to on-chip RAM. This performance and programmability make the C80 ideally suited for video, imaging, and high-speed telecommunications applications.
IEEE Standard 1149.11990, IEEE Standard Test Access Port and Boundary-Scan Architecture
|Part number||Order||Cycle time (ns)||Data/program memory space (words)||DMA (Ch)||MIPS||MOPS||Operating temperature range (C)||Package Group||Rating|
||20||2.4G||1||60||120||-55 to 125||
CFP | 320
CPGA | 305
|SMJ320C80||Samples not available||20||2.4G||1||60||120||-55 to 125||CPGA | 305||Military|