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SN54SC6T07-SEP

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Radiation-tolerant six-bit open-drain fixed-direction level translator

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Data sheet

SN54SC6T07-SEP

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Data sheet Order now

Product details

Technology family SCxT Vout (min) (V) 1.2 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs Input type TTL-Compatible CMOS Output type Open-drain Rating Space Operating temperature range (°C) -55 to 125
Technology family SCxT Vout (min) (V) 1.2 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs Input type TTL-Compatible CMOS Output type Open-drain Rating Space Operating temperature range (°C) -55 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4
  • Vendor item drawing available, VID V62/24617
  • Total ionizing dose characterized at 30 krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2V to 5.5V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2V VCC
    • TTL compatible inputs:
      • Up translation:
        • 1.8-V – Inputs from 1.2V
        • 2.5V – Inputs from 1.8V
        • 3.3V – Inputs from 1.8V, 2.5V
        • 5.0V – Inputs from 2.5V, 3.3V
      • Down translation:

        • 1.2V – Inputs from 1.8V, 2.5V, 3.3V, 5.0V

        • 1.8-V – Inputs from 2.5V, 3.3V, 5.0V
        • 2.5V – Inputs from 3.3V, 5.0V
        • 3.3V – Inputs from 5.0V
  • 5.5V tolerant input pins
  • Output drive up to 25mA AT 5V
  • Latch-up performance exceeds 250mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification
  • Vendor item drawing available, VID V62/24617
  • Total ionizing dose characterized at 30 krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2V to 5.5V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2V VCC
    • TTL compatible inputs:
      • Up translation:
        • 1.8-V – Inputs from 1.2V
        • 2.5V – Inputs from 1.8V
        • 3.3V – Inputs from 1.8V, 2.5V
        • 5.0V – Inputs from 2.5V, 3.3V
      • Down translation:

        • 1.2V – Inputs from 1.8V, 2.5V, 3.3V, 5.0V

        • 1.8-V – Inputs from 2.5V, 3.3V, 5.0V
        • 2.5V – Inputs from 3.3V, 5.0V
        • 3.3V – Inputs from 5.0V
  • 5.5V tolerant input pins
  • Output drive up to 25mA AT 5V
  • Latch-up performance exceeds 250mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification

The SN54SC6T07-SEP device contains six independent buffers with open-drain outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8-V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2V input to 1.8V output or 1.8V input to 3.3V output). Additionally, the 5V tolerant input pins enable down translation (for example 3.3V to 2.5V output).

The SN54SC6T07-SEP device contains six independent buffers with open-drain outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8-V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2V input to 1.8V output or 1.8V input to 3.3V output). Additionally, the 5V tolerant input pins enable down translation (for example 3.3V to 2.5V output).
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Type Title Date
* Data sheet SN54SC6T07-SEP Radiation Tolerant, Hex Open-Drain Buffers with Integrated Translation datasheet PDF | HTML 19 Jan 2024
* Radiation & reliability report SN54SC6T07-SEP Production Flow and Reliability Report PDF | HTML 10 Apr 2024
* Radiation & reliability report SN54SC6T07-SEP Single Event Effects Radiation Report PDF | HTML 21 Feb 2024
* Radiation & reliability report SN54SC6T07-SEP Total Ionizing Dose (TID) Report PDF | HTML 08 Feb 2024

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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TSSOP (PW) 14 View options
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