SN74LS31 Hex Delay Elements for Generating Delay Lines | TI.com

SN74LS31
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Hex Delay Elements for Generating Delay Lines

Hex Delay Elements for Generating Delay Lines - SN74LS31
Datasheet
 

Description

These 'LS31 delay elements are intended to provide well-defined delays across both temperature and VCC ranges. Used in cascade, a limitless range of delay gating is possible.

All inputs are PNP with IIL MAX of -0.2 mA. Gates 1, 2, 5, and 6 have standard Low-Power Schottky output sink current capability of 4 and 8 mA IOL. Buffers 3 and 4 are rated at 12 and 24 mA.

The SN54LS31 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS31 is characterized for operation from 0°C to 70°C.

 

Features

  • Delay Elements for Generating Delay Lines
  • Inverting and Non-inverting Elements
  • Buffer NAND Elements Rated at IOL of 12/24 mA
  • PNP Inputs Reduce Fan-In (IIL = -0.2 mA MAX)
  • Worst Case MIN/MAX Delays Guaranteed Across Temperature and VCC Ranges

 

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) IOL (Max) (mA) IOH (Max) (mA) ICC (uA) Input type Output type Features Data rate (Mbps) Rating Package Group
SN74LS31 Order now LS     4.75     5.25     6     24     -1.2     20000     Bipolar     Push-Pull     High speed (tpd 10-50ns)
Input clamp diode    
70     Catalog     PDIP | 16
SOIC | 16
SO | 16