SN74LVC02A-EP Enhanced Product Quadruple 2-Input Positive-Nor Gate | TI.com

SN74LVC02A-EP (ACTIVE)

Enhanced Product Quadruple 2-Input Positive-Nor Gate

Enhanced Product Quadruple 2-Input Positive-Nor Gate - SN74LVC02A-EP
Datasheet
 

Description

The quadruple 2-input positive-NOR gate is designed for 2.7-V to 3.6-V VCC operation.

The SN74LVC02A performs the Boolean function Y = A + B or Y = AB in positive logic.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

Features

  • Controlled Baseline
    • One Assembly Site
    • One Test Site
    • One Fabrication Site
  • Extended Temperature Performance of -55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval
  • Inputs Accept Voltages to 5.5 V
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Parametrics

Compare all products in NOR gate Email Download to Excel
Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) Inputs per channel IOL (Max) (mA) IOH (Max) (mA) Input type Output type Features Data rate (Max) (Mbps) Rating Operating temperature range (C) Package Group Package size: mm2:W x L (PKG)
SN74LVC02A-EP Order now LVC     2     3.6     4     2     24     -24     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Ultra High Speed (tpd <5ns)    
100     HiRel Enhanced Product     -55 to 125     TSSOP | 14     14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)    
SN54LVC02A Samples not available LVC     2     3.6     4     2     24     -24     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Ultra High Speed (tpd <5ns)    
100     Military     -55 to 125     CDIP | 14
CFP | 14
LCCC | 20    
See datasheet (CDIP)
See datasheet (CFP)
20LCCC: 79 mm2: 8.89 x 8.89 (LCCC | 20)    
SN74LVC02A Order now LVC     1.5     3.6     4     2     24     -24     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Ultra High Speed (tpd <5ns)    
100     Catalog     -40 to 125     SOIC | 14
SO | 14
SSOP | 14
TSSOP | 14
VQFN | 14    
14SO: 80 mm2: 7.8 x 10.2 (SO | 14)
14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)
14SSOP: 48 mm2: 7.8 x 6.2 (SSOP | 14)
14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)
14VQFN: 12 mm2: 3.5 x 3.5 (VQFN | 14)    
SN74LVC02A-Q1 Samples not available LVC     2     3.6     4     2     24     -24     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Very High Speed (tpd 5-10ns)    
100     Automotive     -40 to 125     SOIC | 14
TSSOP | 14    
14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)
14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)