SN74LVC2G14 Dual Schmitt-Trigger Inverter | TI.com

SN74LVC2G14
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Dual Schmitt-Trigger Inverter

 

Description

This dual Schmitt-trigger inverter is designed for
1.65-V to 5.5-V VCC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

The SN74LVC2G14 device contains two inverters and performs the Boolean function Y = A. The device functions as two independent inverters, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

For all available packages, see the orderable addendum at the end of the data sheet.

Features

  • Available in the TI NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.4 ns at 3.3 V
  • Low-Power Consumption, 10-μA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Support Translation Down
    (5 V to 3.3 V; 3.3 V to 1.8 V)
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) IOL (Max) (mA) IOH (Max) (mA) ICC (uA) Input type Output type Features Data rate (Mbps) Rating Package Group
SN74LVC2G14 Order now LVC     1.65     5.5     2     32     -32     10     Schmitt-Trigger     Push-Pull     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
300     Catalog     DSBGA | 6
SC70 | 6
SOT-23 | 6    
SN74AUC1G14 Order now AUC     0.8     2.7     1     9     -9     10     Schmitt-Trigger     Push-Pull     Balanced outputs
Ultra high speed (tpd <5ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
500     Catalog     DSBGA | 5
SC70 | 5
SOT-23 | 5    
SN74AUP1G14 Order now AUP     0.8     3.6     1     4     -4     0.9     Schmitt-Trigger     Push-Pull     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
200     Catalog     DSBGA | 4
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5
SOT-5X3 | 5
X2SON | 5    
SN74LVC1G14 Order now LVC     1.65     5.5     1     32     -32     10     Schmitt-Trigger     Push-Pull     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
300     Catalog     DSBGA | 4
DSBGA | 5
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5
SOT-5X3 | 5
X2SON | 5    
SN74LVC1G240 Order now LVC     1.65     5.5     1     32     -32     10     Standard CMOS     3-State     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
300     Catalog     DSBGA | 5
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5    
SN74LVC2G14-Q1 Samples not available LVC     1.65     5.5     2     32     -32     10     Schmitt-Trigger     Push-Pull     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
300