Product details

Technology family TXS Applications I2C, MDIO, SMbus Bits (#) 8 Data rate (max) (Mbps) 100 High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 1.4 Vout (max) (V) 5.5 IOH (max) (mA) 0 IOL (max) (mA) 0 Supply current (max) (µA) 8 Features Edge rate accelerator, Output enable, Vcc isolation Input type Transmission Gate Output type 3-State, Transmission Gate Rating Catalog Operating temperature range (°C) -40 to 85
Technology family TXS Applications I2C, MDIO, SMbus Bits (#) 8 Data rate (max) (Mbps) 100 High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 1.4 Vout (max) (V) 5.5 IOH (max) (mA) 0 IOL (max) (mA) 0 Supply current (max) (µA) 8 Features Edge rate accelerator, Output enable, Vcc isolation Input type Transmission Gate Output type 3-State, Transmission Gate Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (NME) 20 7.5 mm² 2.5 x 3 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4 VQFN (RGY) 20 15.75 mm² 4.5 x 3.5
  • No Direction-Control Signal Needed
  • Maximum Data Rates
    • 110 Mbps (Push Pull)
    • 1.2 Mbps (Open Drain)
  • 1.4 V to 3.6 V on A Port and 1.65 V to 5.5 V on B Port (V CCA ≤ V CCB)
  • No Power-Supply Sequencing Required – Either V CCA or V CCB Can Be Ramped First
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22 (A Port)
    • 2000 V Human Body Model (A114-B)
    • 150 V Machine Model (A115-A)
    • 1000 V Charged-Device Model (C101)
  • IEC 61000-4-2 ESD (B Port)
    • ±8 kV Contact Discharge
    • ±6 kV Air-Gap Discharge
  • No Direction-Control Signal Needed
  • Maximum Data Rates
    • 110 Mbps (Push Pull)
    • 1.2 Mbps (Open Drain)
  • 1.4 V to 3.6 V on A Port and 1.65 V to 5.5 V on B Port (V CCA ≤ V CCB)
  • No Power-Supply Sequencing Required – Either V CCA or V CCB Can Be Ramped First
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22 (A Port)
    • 2000 V Human Body Model (A114-B)
    • 150 V Machine Model (A115-A)
    • 1000 V Charged-Device Model (C101)
  • IEC 61000-4-2 ESD (B Port)
    • ±8 kV Contact Discharge
    • ±6 kV Air-Gap Discharge

This device is a 8-bit non-inverting level translator which uses two separate configurable power-supply rails. The A port tracks the V CCA pin supply voltage. The V CCA pin accepts any supply voltage between 1.4 V and 3.6 V. The B port tracks the V CCB pin supply voltage. The V CCB pin accepts any supply voltage between 1.65 V and 5.5 V. Two input supply pins allows for low Voltage bidirectional translation between any of the 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V voltage nodes.

When the output-enable (OE) input is low, all outputs are placed in the high-impedance (Hi-Z) state.

To ensure the Hi-Z state during power-up or power-down periods, tie OE to GND through a pull-down resistor. The minimum value of the resistor is determined by the current-sourcing capability of the driver.

This device is a 8-bit non-inverting level translator which uses two separate configurable power-supply rails. The A port tracks the V CCA pin supply voltage. The V CCA pin accepts any supply voltage between 1.4 V and 3.6 V. The B port tracks the V CCB pin supply voltage. The V CCB pin accepts any supply voltage between 1.65 V and 5.5 V. Two input supply pins allows for low Voltage bidirectional translation between any of the 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V voltage nodes.

When the output-enable (OE) input is low, all outputs are placed in the high-impedance (Hi-Z) state.

To ensure the Hi-Z state during power-up or power-down periods, tie OE to GND through a pull-down resistor. The minimum value of the resistor is determined by the current-sourcing capability of the driver.

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Technical documentation

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Type Title Date
* Data sheet TXS0108E 8-Bit Bidirectional Voltage-Level Shifter For Open-Drain And Push-Pull datasheet (Rev. I) 25 Jul 2023
Application brief Integrated vs. Discrete Open Drain Level Translation PDF | HTML 09 Jan 2024
Application note Leveraging Edge Rate Accelerators with Auto-Sensing Level Shifters PDF | HTML 29 Sep 2023
Application brief Future-Proofing Your Level Shifter Design with TI's Dual Footprint Packages PDF | HTML 05 Sep 2023
Application note Do’s and Don’ts for TXB and TXS Voltage Level-Shifters with Edge Rate Accelerato PDF | HTML 28 Jun 2023
Product overview Voltage Translation Application Quick Reference PDF | HTML 28 Jun 2022
EVM User's guide TXS-EVM User's Guide (Rev. B) PDF | HTML 08 Jun 2021
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Application note Effects of pullup and pulldown resistors on TXS and TXB devices (Rev. A) 28 Mar 2018
Application note A Guide to Voltage Translation With TXS-Type Translators 29 Jun 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
Not available on TI.com
Evaluation board

TXS-EVM — Translator family evaluation module for single-, dual-, quad- and octal-channel devices

The TXS-EVM is designed to support single, dual, quad and octal channel TXS devices. The TXS devices belong to the auto bidirectional voltage level translation family with an operating voltage between 1.2V and 5.5 V designed to support various generic voltage level translation applications across (...)

User guide: PDF | HTML
Not available on TI.com
Simulation model

TXS0108E IBIS Model (Rev. A)

SCEM547A.ZIP (167 KB) - IBIS Model
Reference designs

TIDA-00352 — SDI Video Aggregation Reference Design

This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is (...)
Test report: PDF
Schematic: PDF
Package Pins Download
NFBGA (NME) 20 View options
TSSOP (PW) 20 View options
VQFN (RGY) 20 View options

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