CD74HC10 High Speed CMOS Logic Triple 3-Input NAND Gates |


High Speed CMOS Logic Triple 3-Input NAND Gates

High Speed CMOS Logic Triple 3-Input NAND Gates - CD74HC10


The ’HC10 and ’HCT10 logic gates utilize silicon gate CMOS technology to achieve operating s peeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally pin compatible with the standard LS logic family.


  • Buffered Inputs
  • Typical Propagation Delay: 8ns at VCC = 5V, CL = 15pF, TA = 25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs...10 LSTTL Loads
    • Bus Driver Outputs...15 LSTTL Loads
  • Wide Operating Temperature Range...–55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

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Parametrics Compare all products in NAND gate

Technology Family
VCC (Min) (V)
VCC (Max) (V)
Channels (#)
Inputs per channel
IOL (Max) (mA)
IOH (Max) (mA)
Input type
Output type
Data rate (Max) (Mbps)
Operating temperature range (C)
Package Group
Package size: mm2:W x L (PKG)
CD74HC10 CD54HC10
HC     HC    
2     2    
6     6    
5.2     5.2    
-5.2     -5.2    
Standard CMOS     Standard CMOS    
Push-Pull     Push-Pull    
High Speed (tpd 10-50ns)      
Catalog     Military    
-55 to 125     -55 to 125    
PDIP | 14
SOIC | 14    
CDIP | 14    
See datasheet (PDIP)
14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)    
See datasheet (CDIP)