TMS320C6414

Name: TMS320C6414
Brand: TI
SKU: TMS320C6414
Price: 85.55 USD

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DSP de punto fijo C64x de hasta 720 MHz, con McBSP

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Hoja de datos

document-pdfAcrobat TMS320C6414, TMS320C6415, TMS320C6416 Fixed-Point Digital Signal Processors datasheet (Rev. N) (Inglés)

Errata

document-pdfAcrobat
TMS320C6414/C6415/C6416 Silicon Errata (Silicon Rev. 1.0,1.01,1.02,1.03,1.1,2.0) (Rev. T) (Inglés)

TMS320C6414

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Detalles del producto

DSP type

1 C64x

DSP (max) (MHz)

500, 600, 720

CPU

32-/64-bit

Operating system

DSP/BIOS

Rating

Catalog

Operating temperature range (°C)

-40 to 105

DSP type

1 C64x

DSP (max) (MHz)

500, 600, 720

CPU

32-/64-bit

Operating system

DSP/BIOS

Rating

Catalog

Operating temperature range (°C)

-40 to 105

FCBGA (GLZ)

532

529 mm² 23 x 23

FCBGA (ZLZ)

532

529 mm² 23 x 23

Highest-Performance Fixed-Point Digital Signal Processors (DSPs)
- 2-, 1.67-, 1.39-ns Instruction Cycle Time
- 500-, 600-, 720-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- Twenty-Eight Operations/Cycle
- 4000, 4800, 5760 MIPS
- Fully Software-Compatible With C62x™
- C6414/15/16 Devices Pin-Compatible
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
  - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Non-Aligned Load-Store Architecture
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2™ Increased Orthogonality
Viterbi Decoder Coprocessor (VCP) [C6416]
- Supports Over 600 7.95-Kbps AMR
- Programmable Code Parameters
Turbo Decoder Coprocessor (TCP) [C6416]
- Supports up to 7 2-Mbps or 43 384-Kbps 3GPP (6 Iterations)
- Programmable Turbo Code and Decoding Parameters
L1/L2 Memory Architecture
- 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
- 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
- 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
Two External Memory Interfaces (EMIFs)
- One 64-Bit (EMIFA), One 16-Bit (EMIFB)
- Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
- 1280M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
Host-Port Interface (HPI)
- User-Configurable Bus Width (32-/16-Bit)
32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415/C6416 ]
- Three PCI Bus Address Registers:
  Prefetchable Memory
  Non-Prefetchable Memory I/O
- Four-Wire Serial EEPROM Interface
- PCI Interrupt Request Under DSP Program Control
- DSP Interrupt Via PCI I/O Cycle
Three Multichannel Buffered Serial Ports
- Direct Interface to T1/E1, MVIP, SCSA Framers
- Up to 256 Channels Each
- ST-Bus-Switching-, AC97-Compatible
- Serial Peripheral Interface (SPI) Compatible (Motorola™)
Three 32-Bit General-Purpose Timers
Universal Test and Operations PHY Interface for ATM (UTOPIA) [C6415/C6416]
- UTOPIA Level 2 Slave ATM Controller
- 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
- User-Defined Cell Format up to 64 Bytes
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
532-Pin Ball Grid Array (BGA) Package (GLZ, ZLZ and CLZ Suffixes), 0.8-mm Ball Pitch
0.13-µm/6-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.2-V/1.25-V Internal (500 MHz)
3.3-V I/Os, 1.4-V Internal (600 and 720 MHz)

C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Other trademarks are the property of their respective owners.
Throughout the remainder of this document, the TMS320C6414, TMS320C6415, and TMS320C6416 shall be referred to as TMS320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414, C6415, or C6416.
These C64xdevices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name.

Highest-Performance Fixed-Point Digital Signal Processors (DSPs)
- 2-, 1.67-, 1.39-ns Instruction Cycle Time
- 500-, 600-, 720-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- Twenty-Eight Operations/Cycle
- 4000, 4800, 5760 MIPS
- Fully Software-Compatible With C62x™
- C6414/15/16 Devices Pin-Compatible
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
  - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Non-Aligned Load-Store Architecture
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2™ Increased Orthogonality
Viterbi Decoder Coprocessor (VCP) [C6416]
- Supports Over 600 7.95-Kbps AMR
- Programmable Code Parameters
Turbo Decoder Coprocessor (TCP) [C6416]
- Supports up to 7 2-Mbps or 43 384-Kbps 3GPP (6 Iterations)
- Programmable Turbo Code and Decoding Parameters
L1/L2 Memory Architecture
- 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
- 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
- 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
Two External Memory Interfaces (EMIFs)
- One 64-Bit (EMIFA), One 16-Bit (EMIFB)
- Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
- 1280M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
Host-Port Interface (HPI)
- User-Configurable Bus Width (32-/16-Bit)
32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415/C6416 ]
- Three PCI Bus Address Registers:
  Prefetchable Memory
  Non-Prefetchable Memory I/O
- Four-Wire Serial EEPROM Interface
- PCI Interrupt Request Under DSP Program Control
- DSP Interrupt Via PCI I/O Cycle
Three Multichannel Buffered Serial Ports
- Direct Interface to T1/E1, MVIP, SCSA Framers
- Up to 256 Channels Each
- ST-Bus-Switching-, AC97-Compatible
- Serial Peripheral Interface (SPI) Compatible (Motorola™)
Three 32-Bit General-Purpose Timers
Universal Test and Operations PHY Interface for ATM (UTOPIA) [C6415/C6416]
- UTOPIA Level 2 Slave ATM Controller
- 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
- User-Defined Cell Format up to 64 Bytes
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
532-Pin Ball Grid Array (BGA) Package (GLZ, ZLZ and CLZ Suffixes), 0.8-mm Ball Pitch
0.13-µm/6-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.2-V/1.25-V Internal (500 MHz)
3.3-V I/Os, 1.4-V Internal (600 and 720 MHz)

The TMS320C64x™ DSPs (including the TMS320C6414, TMS320C6415, and TMS320C6416 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C64x™ (C64x™) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™ developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI™ architecture. The C64x can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5760 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6416 device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 600 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to forty-three 384-Kbps or seven 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.

The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port (C6415/C6416 only); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415/C6416 only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.

The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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Documentación técnica

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	Tipo	Título		Fecha
*	Data sheet	TMS320C6414, TMS320C6415, TMS320C6416 Fixed-Point Digital Signal Processors datasheet (Rev. N)		26 may 2005
*	Errata	TMS320C6414/C6415/C6416 Silicon Errata (Silicon Rev. 1.0,1.01,1.02,1.03,1.1,2.0) (Rev. T)		01 ago 2007
	Application note	How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)	PDF \| HTML	19 may 2021
	User guide	Emulation and Trace Headers Technical Reference Manual (Rev. I)		09 ago 2012
	Application note	Introduction to TMS320C6000 DSP Optimization		06 oct 2011
	User guide	TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J)		30 jul 2010
	User guide	TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q)		02 jul 2009
	Application note	Migrating from TMS320C6416/15/14 to TMS320C6416T/15T/14T (Rev. B)		22 feb 2008
	Application note	TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)		04 sep 2007
	User guide	TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E)		11 abr 2007
	Product overview	TMS320C6000 DSP TCP/IP Stack Software (Rev. C)		04 abr 2007
	User guide	TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G)		14 dic 2006
	User guide	TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C)		15 nov 2006
	User guide	TMS320C64x DSP Two-Level Internal Memory Reference Guide (Rev. C)		28 feb 2006
	User guide	TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C)		01 ene 2006
	Application note	TMS320C6414 Hardware Designer's Resource Guide (Rev. A)		22 oct 2005
	Application note	Migrating from TMS320C64x to TMS320C64x+ (Rev. A)		20 oct 2005
	Application note	TMS320C6000 EMIF to USB Interfacing Using Cypress EZ-USB SX2 (Rev. A)		20 may 2005
	User guide	TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C)		01 mar 2005
	User guide	TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B)		25 ene 2005
	Application note	Migrating From TMS320C6416/15/14/11 Rev 1.1 to Rev 2.0		19 oct 2004
	Application note	Use and Handling of Semiconductor Packages With ENIG Pad Finishes		31 ago 2004
	User guide	TMS320C6000 Chip Support Library API Reference Guide (Rev. J)		13 ago 2004
	Application note	TMS320C64x Reference Design		12 may 2004
	Application note	TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)		26 abr 2004
	Application note	TMS320C6000 Board Design: Considerations for Debug (Rev. C)		21 abr 2004
	User guide	TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A)		25 mar 2004
	Application note	TMS320C6000 McBSP Initialization (Rev. C)		08 mar 2004
	Application note	TMS320C6000 EDMA IO Scheduling and Performance		05 mar 2004
	Application note	TMS320C64x DSP Peripheral Component Interconnect (PCI) Performance		31 oct 2003
	Application note	TMS320C64x DSP Host Port Interface (HPI) Performance		24 oct 2003
	Application note	Tips for Using the EDMA with the Utopia Port		15 sep 2003
	User guide	TMS320C6000 DSP Designing for JTAG Emulation Reference Guide		31 jul 2003
	Application note	TMS320C6414/5/6 Power Consumption Summary (Rev. C)		30 jun 2003
	User guide	TMS320C6000 DSP Cache User's Guide (Rev. A)		05 may 2003
	Application note	Using IBIS Models for Timing Analysis (Rev. A)		15 abr 2003
	Application note	How to Begin Development Today With the TMS320C6414, C6415, and C6416 DSPs (Rev. A)		06 mar 2003
	Application note	TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)		04 jun 2002
	Application note	TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C)		17 abr 2002
	Application note	TMS320C6000 Board Design for JTAG (Rev. C)		02 abr 2002
	Application note	TMS320C6000 EMIF to External Flash Memory (Rev. A)		13 feb 2002
	Application note	Cache Usage in High-Performance DSP Applications with the TMS320C64x		13 dic 2001
	Application note	Using a TMS320C6000 McBSP for Data Packing (Rev. A)		31 oct 2001
	Application note	TMS320C6000 Enhanced DMA: Example Applications (Rev. A)		24 oct 2001
	Application note	Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A)		30 sep 2001
	Application note	TMS320C6000 Host Port to MC68360 Interface (Rev. A)		30 sep 2001
	Application note	TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)		31 ago 2001
	Application note	TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A)		31 ago 2001
	Application note	Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)		31 ago 2001
	Application note	TMS320C6000 System Clock Circuit Example (Rev. A)		15 ago 2001
	Application note	TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)		23 jul 2001
	Application note	TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A)		10 jul 2001
	Application note	TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)		30 jun 2001
	Application note	TMS320C6000 Host Port to MPC860 Interface (Rev. A)		21 jun 2001
	Application note	TMS320C6000 McBSP: IOM-2 Interface (Rev. A)		21 may 2001
	Application note	TMS320C6415/6416: Using PCI EEPROM Interface and McBSP2 in a Single System		01 mar 2001
	User guide	TMS320C64x Technical Overview (Rev. B)		30 ene 2001
	Application note	Circular Buffering on TMS320C6000 (Rev. A)		12 sep 2000
	Application note	TMS320C6000 McBSP as a TDM Highway (Rev. A)		11 sep 2000
	Application note	TMS320C6000 u-Law and a-Law Companding with Software or the McBSP		02 feb 2000
	Application note	General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point		31 ene 2000
	Application note	TMS320C6000 C Compiler: C Implementation of Intrinsics		07 dic 1999
	Application note	TMS320C6000 McBSP: I2S Interface		08 sep 1999

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Sonda de depuración

TMDSEMU560V2STM-U — Sonda de depuración USB de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

No disponible en TI.com

Sonda de depuración

TMDSEMU560V2STM-UE — Sonda de depuración USB y ethernet de seguimiento del sistema XDS560v2

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

No disponible en TI.com

Software de aplicación y estructura

SPRC137 — TMS320C6414/C6415/C6416 Diseño de referencia

TI provides a reference design with commonly used configurations that allow customers to get maximum performance effortlessly from TMS320C64x™ DSP based systems. For extreme high performance, an SDRAM only interface is designed to run at speeds up to 150 MHz. The reference design also includes a (...)

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Controlador o biblioteca

AEC-AER — Acoustic echo cancellation/removal for TI C64x+, C674x, C55x and Cortex®-A8 processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

Productos y hardware compatibles

Productos

Procesadores basados en Arm

66AK2G12 — DSP+Arm multinúcleo de alto rendimiento: 1x Arm, núcleos A15, 1x C66x DSP núcleo

Procesadores digitales de señales (DSP)

DM505 — SoC para Vision Analytics, encapsulado de 15 mm

SM320C6201-EP — DSP de punto fijo C6201 de producto mejorado

SM320C6415 — DSP de punto fijo C64x de calidad militar

SM320C6415-EP — DSP de punto fijo C6415 de producto mejorado

SM320C6424-EP — DSP de punto fijo C6424 de producto mejorado

SM320C6455-EP — DSP de punto fijo C6455 de producto mejorado

SM320C6472-HIREL — DSP de punto fijo C6472 de 6 núcleos de producto de alta confiabilidad

SM320C6678-HIREL — DSP de punto flotante y fijo C6678 de 8 núcleos de alto rendimiento y de producto de alta confiabili

SM320C6701 — DSP de punto flotante C67x de núcleo único para aplicaciones militares, de hasta 167 MHz

SM320C6701-EP — DSP de punto flotante C6701 de producto mejorado

SM320C6711D-EP — DSP de punto flotante C6711D de producto mejorado

SM320C6712D-EP — DSP C6712D de producto mejorado

SM320C6713B-EP — DSP de punto flotante C6713 de producto mejorado

SM320C6727B — DSP de punto flotante C6727B de calidad militar

SM320C6727B-EP — DSP de punto flotante C6727 de producto mejorado

SM320DM642-HIREL — DSP DM642 de medios digitales de productos de alta confiabilidad

SM32C6416T-EP — DSP de punto fijo C6416T de producto mejorado

SMJ320C6201B — Procesador de señal digital de punto fijo, de calidad militar

SMJ320C6203 — DSP de punto fijo de calidad militar C62x: encapsulado cerámico

SMJ320C6415 — DSP de punto fijo de calidad militar C64x: encapsulado cerámico

SMJ320C6701 — DSP de punto flotante de calidad militar C67x: encapsulado cerámico

SMJ320C6701-SP — DSP de punto flotante de calidad espacial C6701: clase V tolerante a radiación con encapsulado cerám

SMV320C6727B-SP — DSP de punto flotante de calidad espacial C6727B: clase V tolerante a radiación con encapsulado cerá

TMS320C5517 — DSP de punto fijo C55x de baja potencia y hasta 200 MHz, con USB, interfaz LCD, FFT HWA y SAR ADC

TMS320C5532 — DSP de punto fijo C55x de baja potencia y hasta 100 MHz

TMS320C5533 — DSP de punto fijo C55x de baja potencia y hasta 100 MHz, con USB

TMS320C5534 — DSP de punto fijo C55x de baja potencia y hasta 100 MHz, con interfaz LCD

TMS320C5535 — DSP de punto fijo C55x de baja potencia y hasta 100MHz, con USB, interfaz LCD, FFT HWA y SAR ADC

TMS320C6201 — Procesador de señal digital de punto fijo

TMS320C6202 — Procesador de señal digital de punto fijo

TMS320C6202B — DSP de punto fijo C62x de hasta 300 MHz y 384 KB

TMS320C6203B — DSP de punto fijo C62x de hasta 300 MHz y 896 KB

TMS320C6204 — Procesador de señal digital de punto fijo

TMS320C6205 — Procesador de señal digital de punto fijo

TMS320C6211B — DSP de punto fijo C62x de hasta 167 MHz

TMS320C6411 — DSP de punto fijo C64x de hasta 300 MHz, con McBSP

TMS320C6414 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP

TMS320C6415 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP y PCI

TMS320C6416 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP, PCI y VCP/TCP

TMS320C6421Q — DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 8 bits y DDR2 de 16 bits

TMS320C6424Q — DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 16/8 bits y DDR2 de 32/16 bits

TMS320C6454 — DSP de punto fijo C64x+ de hasta 1 GHz, con EMIFA de 64 bits, DDR2 de 32/16 bits y Ethernet de 1 Gbp

TMS320C6457 — Procesador de señal digital de infraestructura de comunicaciones

TMS320C6701 — DSP de punto flotante C67x de hasta 167 MHz, con McBSP

TMS320C6711D — DSP de punto flotante C67x de hasta 250 MHz, con McBSP y EMIFA de 32 bits

TMS320C6712D — DSP de punto flotante C67x de hasta 150 MHz, con McBSP y EMIFA de 16 bits

TMS320C6720 — DSP de punto flotante C67x de hasta 200 MHz, con McASP y EMIFA de 16 bits

TMS320C6722B — DSP de punto flotante C67x de hasta 250 MHz, con McASP y EMIFA de 16 bits

TMS320C6726B — DSP de punto flotante C67x de hasta 266 MHz, con McASP y EMIFA de 16 bits

TMS320C6727 — DSP de punto flotante C67x de hasta 250MHz, con McASP y EMIFA de 32 bits

TMS320C6727B — DSP de punto flotante C67x de hasta 350 MHz, con McASP y EMIFA de 32 bits

TMS320C6743 — DSP de punto flotante C674x de 375 MHz y baja potencia

TMS320C6745 — DSP de punto flotante C674x de 456 MHz y baja potencia, con QFP

TMS320C6747 — DSP de punto flotante C674x de 456 MHz y baja potencia, con PBGA

TMS320DM642Q — Procesador de señal digital de punto fijo de imágenes y video

TMS320DM6431Q — Procesador de medios digitales de hasta 2,400 MIPS y velocidad de reloj de 300 MHz

TMS320DM6435Q — Procesador de medios digitales de hasta 4,800 MIPS y velocidad de reloj de 600 MHz, con 1 McASP y 1

TMS320DM6437Q — Procesador de medios digitales de hasta 4,800 MIPS y velocidad de reloj de 600 MHz, con 1 McASP y 2

TMS320DM6441 — Sistema de medios digitales en chip DaVinci

TMS320DM6467T — Sistema de medios digitales en chip

TMS320DM647 — Procesador de medios digitales

Opciones de descarga

Controlador o biblioteca

FAXLIB — FAX library (FAXLIB) for C66x, C64x+ and C55x processors