Inicio Microcontroladores (MCU) y procesadores Procesadores digitales de señales (DSP)
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Microcontroladores (MCU) y procesadores
Procesadores digitales de señales (DSP)

TMS320C6424

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DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 16/8 bits, DDR2 de 32/16 bits y SDRAM

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TMS320C6424

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Detalles del producto

DSP type 1 C64x+ DSP (max) (MHz) 400, 500, 600 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) -40 to 105
DSP type 1 C64x+ DSP (max) (MHz) 400, 500, 600 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) -40 to 105
BGA (ZDU) 376 529 mm² 23 x 23 NFBGA (ZWT) 361 256 mm² 16 x 16
  • High-Performance Digital Signal Processor (C6424)
    • 2.5-, 2-, 1.67, 1.43-ns Instruction Cycle Time
    • 400-, 500-, 600-MHz C64x+™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 3200, 4000, 4800, 5600 MIPS
    • Fully Software-Compatible With C64x
    • Commercial and Automotive (Q or S suffix)Grades
    • Low-Power Device (L suffix)
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
    • C64x+ Extensions
      • Compact 16-bit Instructions
      • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
    • 640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Endianess: Supports Both Little Endian and Big Endian
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Supports up to 333-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
    • Asynchronous 16-Bit Wide EMIF (EMIFA) With up to 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Two UARTs (One with RTS and CTS Flow Control)
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2S and TDM
    • AC97 Audio Codec Interface
    • SPI
    • Standard Voice Codec Interface (AIC12)
    • Telecom Interfaces - ST-Bus, H-100
    • 128 Channel Mode
  • Multichannel Audio Serial Port (McASP0)
    • Four Serializers and SPDIF (DIT) Mode
  • 16-Bit Host-Port Interface (HPI)
  • 32-Bit 33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports Multiple Media Independent Interfaces (MII, RMII)
    • Management Data Input/Output (MDIO) Module
  • VLYNQ™ Interface (FPGA Interface)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ROM Bootloader
  • Individual Power-Savings Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Packages:
    • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
    • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-Q6/-Q5/-Q4)
  • 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
  • APPLICATIONS
    • Telecom
    • Audio
    • Industrial Applications
  • Community Reesources

All trademarks are the property of their respective owners.
  • High-Performance Digital Signal Processor (C6424)
    • 2.5-, 2-, 1.67, 1.43-ns Instruction Cycle Time
    • 400-, 500-, 600-MHz C64x+™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 3200, 4000, 4800, 5600 MIPS
    • Fully Software-Compatible With C64x
    • Commercial and Automotive (Q or S suffix)Grades
    • Low-Power Device (L suffix)
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
    • C64x+ Extensions
      • Compact 16-bit Instructions
      • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
    • 640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Endianess: Supports Both Little Endian and Big Endian
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Supports up to 333-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
    • Asynchronous 16-Bit Wide EMIF (EMIFA) With up to 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Two UARTs (One with RTS and CTS Flow Control)
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2S and TDM
    • AC97 Audio Codec Interface
    • SPI
    • Standard Voice Codec Interface (AIC12)
    • Telecom Interfaces - ST-Bus, H-100
    • 128 Channel Mode
  • Multichannel Audio Serial Port (McASP0)
    • Four Serializers and SPDIF (DIT) Mode
  • 16-Bit Host-Port Interface (HPI)
  • 32-Bit 33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports Multiple Media Independent Interfaces (MII, RMII)
    • Management Data Input/Output (MDIO) Module
  • VLYNQ™ Interface (FPGA Interface)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ROM Bootloader
  • Individual Power-Savings Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Packages:
    • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
    • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-Q6/-Q5/-Q4)
  • 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
  • APPLICATIONS
    • Telecom
    • Audio
    • Industrial Applications
  • Community Reesources

All trademarks are the property of their respective owners.

The TMS320C64x+™ DSPs (including the TMS320C6424 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6424 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital signal processor applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in telecom, audio, and industrial applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The C6424 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The C6424 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; two multichannel buffered serial ports (McBSPs); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purposeinput/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 peripheral component interconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6424 and the network. The C6424 EMAC supports 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow C6424 to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The C6424 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C64x+™ DSPs (including the TMS320C6424 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6424 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital signal processor applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in telecom, audio, and industrial applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The C6424 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The C6424 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; two multichannel buffered serial ports (McBSPs); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purposeinput/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 peripheral component interconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6424 and the network. The C6424 EMAC supports 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow C6424 to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The C6424 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.
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Documentación técnica

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Tipo Título Fecha
* Data sheet TMS320C6424 Fixed-Point Digital Signal Processor datasheet (Rev. D) 11 ene 2010
* Errata TMS320C6424/21 Digital Signal Processor Silicon Errata (Revs 1.3 1.2 1.1 & 1.0) (Rev. D) 12 ago 2011
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 19 may 2021
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 01 jun 2020
Application note Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 13 ago 2015
Application note Using the TMS320C642x Bootloader (Rev. B) 23 mar 2012
Application note TMS320C642x Power Consumption Summary (Rev. D) 17 feb 2012
Application note Introduction to TMS320C6000 DSP Optimization 06 oct 2011
User guide TMS320C642x DSP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. D) 25 mar 2011
User guide TMS320C642x DSP DDR2 Memory Controller User's Guide (Rev. B) 12 ene 2011
User guide TMS320C642x DSP EMAC/MDIO User's Guide (Rev. C) 23 dic 2010
User guide TMS320C642x DSP Pulse-Width Modulator (PWM) User's Guide (Rev. B) 05 ago 2010
User guide TMS320C642x DSP 64-Bit Timer User's Guide (Rev. A) 03 ago 2010
User guide TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 03 ago 2010
User guide TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 30 jul 2010
User guide TMS320C642x DSP Peripheral Component Interconnect (PCI) User's Guide (Rev. C) 14 may 2010
User guide TMS320C642x DSP Universal Asynchronous Receiver/Transmitter (UART) User's Guide (Rev. C) 15 dic 2009
User guide TMS320C642x DSP Asynchronous External Memory Interface (EMIF) User's Guide (Rev. B) 24 feb 2009
User guide TMS320C64x+ DSP Cache User's Guide (Rev. B) 11 feb 2009
Application note Implementing DDR2 PCB Layout on the TMS320C6424 DSP 16 oct 2008
Application note 12Vin C642x Power using Integrated-FET DC/DC Converters and LDO 09 oct 2008
Application note 5Vin C642x Power using a PMIC (Multi-output DC/DC Converter) 09 oct 2008
Application note TMS320C620x/C642x McBSP: UART (Rev. C) 09 sep 2008
Application note Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) 21 ago 2008
Application note Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 17 jul 2008
User guide TMS320C642x DSP Host Port Interface (HPI) User's Guide (Rev. A) 16 jul 2008
User guide TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A) 05 may 2008
User guide TMS320C642x DSP General-Purpose Input/Output (GPIO) User's Guide (Rev. A) 18 mar 2008
User guide TMS320C642x DSP Multichannel Audio Serial Port (McASP) User's Guide (Rev. C) 13 mar 2008
User guide TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B) 06 mar 2008
User guide TMS320C642x DSP Enhanced DMA (EDMA) Controller User's Guide (Rev. A) 03 mar 2008
User guide TMS320C642x DSP Power and Sleep Controller (PSC) User's Guide (Rev. A) 05 feb 2008
User guide TMS320C642x DSP Phase-Locked Loop Controller (PLLC) User's Guide (Rev. B) 12 dic 2007
Application note Using DMA with Framework Components for C64x+ (Rev. A) 29 oct 2007
User guide TMS320C642x DSP VLYNQ Port User's Guide (Rev. B) 20 sep 2007
User guide TMS320C642x DSP Multichannel Buffered Serial Port (McBSP) User's Guide (Rev. B) 17 sep 2007
Application note TMS320C642x Pin Multiplexing Utility 09 jul 2007
Application note Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 20 may 2007
User guide TMS320C642x DSP Peripherals Overview Reference Guide 04 mar 2007
User guide TMS320C64x+ DSP Big-Endian Library Programmer's Reference 10 mar 2006
User guide TMS320C64x+ Image/Video Processing Library Programmer's Reference 10 mar 2006
Application note Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 20 oct 2005
Test report Download: C64x+ Benchmarks (v1.00) 06 jul 2005

Diseño y desarrollo

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TMDSEMU200-U — Sonda de depuración XDS200 USB

El XDS200 es una sonda de depuración (emulador) que se utiliza para depurar dispositivos integrados de TI. El XDS200 presenta un equilibrio de bajo costo con buen rendimiento en comparación con el XDS110 de bajo costo y el XDS560v2 de alto rendimiento. Es compatible con una amplia (...)

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Sonda de depuración

TMDSEMU560V2STM-U — Sonda de depuración USB de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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Sonda de depuración

TMDSEMU560V2STM-UE — Sonda de depuración USB y ethernet de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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Controlador o biblioteca

SPRC122 — C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

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Productos
Procesadores digitales de señales (DSP)
SM320C6201-EP — DSP de punto fijo C6201 de producto mejorado SM320C6455-EP — DSP de punto fijo C6455 de producto mejorado SMJ320C6201B — Procesador de señal digital de punto fijo, de calidad militar SMJ320C6203 — DSP de punto fijo de calidad militar C62x: encapsulado cerámico TMS320C6201 — Procesador de señal digital de punto fijo TMS320C6202 — Procesador de señal digital de punto fijo TMS320C6202B — DSP de punto fijo C62x de hasta 300 MHz y 384 KB TMS320C6203B — DSP de punto fijo C62x de hasta 300 MHz y 896 KB TMS320C6204 — Procesador de señal digital de punto fijo TMS320C6205 — Procesador de señal digital de punto fijo TMS320C6211B — DSP de punto fijo C62x de hasta 167 MHz TMS320C6411 — DSP de punto fijo C64x de hasta 300 MHz, con McBSP TMS320C6412 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP, McASP, I2cC y Ethernet TMS320C6414 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP TMS320C6414T — DSP de punto fijo C64x de hasta 1 GHz, con McBSP TMS320C6415 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP y PCI TMS320C6415T — DSP de punto fijo C64x de hasta 850 MHz, con McBSP y PCI TMS320C6416 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP, PCI y VCP/TCP TMS320C6416T — DSP de punto fijo C64x de hasta 850 MHz, con McBSP, PCI y VCP/TCP TMS320C6421 — DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 8 bits, DDR2 de 16 bits y SDRAM TMS320C6421Q — DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 8 bits y DDR2 de 16 bits TMS320C6424 — DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 16/8 bits, DDR2 de 32/16 bits y SDRAM TMS320C6424Q — DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 16/8 bits y DDR2 de 32/16 bits TMS320C6452 — DSP de punto fijo C64x+ de hasta 900 MHz, con Ethernet de 1 Gbps TMS320C6454 — DSP de punto fijo C64x+ de hasta 1 GHz, con EMIFA de 64 bits, DDR2 de 32/16 bits y Ethernet de 1 Gbp TMS320C6455 — DSP de punto fijo C64x+ de hasta 1.2 GHz, con EMIFA de 64 bits, DDR2 de 32/16 bits y Ethernet de 1 G TMS320C6457 — Procesador de señal digital de infraestructura de comunicaciones TMS320C6474 — Procesador de señal digital multinúcleo TMS320DM640 — Procesador de señal digital de punto fijo de imágenes y video TMS320DM641 — Procesador de señal digital de punto fijo de imágenes y video TMS320DM642 — Procesador de señal digital de punto fijo de imágenes y video TMS320DM642Q — Procesador de señal digital de punto fijo de imágenes y video TMS320DM6431 — Procesador de medios digitales TMS320DM6431Q — Procesador de medios digitales de hasta 2,400 MIPS y velocidad de reloj de 300 MHz TMS320DM6433 — Procesador de medios digitales TMS320DM6435 — Procesador de medios digitales TMS320DM6435Q — Procesador de medios digitales de hasta 4,800 MIPS y velocidad de reloj de 600 MHz, con 1 McASP y 1  TMS320DM6437 — Procesador de medios digitales TMS320DM6437Q — Procesador de medios digitales de hasta 4,800 MIPS y velocidad de reloj de 600 MHz, con 1 McASP y 2  TMS320DM6441 — Sistema de medios digitales en chip DaVinci TMS320DM6443 — Sistema de medios digitales en chip DaVinci TMS320DM6446 — Sistema de medios digitales en chip DaVinci
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Controlador o biblioteca

SPRC264 — TMS320C5000/6000 Biblioteca de imágenes (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Guía del usuario: PDF
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Controlador o biblioteca

SPRC265 — TMS320C6000 Biblioteca DSP (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Guía del usuario: PDF
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Controlador o biblioteca

TELECOMLIB — Bibliotecas de telecomunicaciones y medios: FAXLIB, VoLIB y AEC/AER para procesadores TMS320C64x+ y

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
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IDE, configuración, compilador o depurador

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

Productos y hardware compatibles

Productos y hardware compatibles

Este recurso de diseño es compatible con la mayoría de los productos de estas categorías.

Revise la página de detalles del producto para verificar la compatibilidad.
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Modelo de simulación

C6424 ZDU BSDL Model (Rev. A)

SPRM250A.ZIP (10 KB) - BSDL Model
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Modelo de simulación

C6424 ZDU IBIS Model (Rev. B)

SPRM241B.ZIP (267 KB) - IBIS Model
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Modelo de simulación

C6424 ZWT BSDL Model (Rev. A)

SPRM251A.ZIP (10 KB) - BSDL Model
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Modelo de simulación

C6424 ZWT IBIS Model (Rev. C)

SPRM240C.ZIP (267 KB) - IBIS Model
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Herramienta de diseño

PROCESSORS-3P-SEARCH — MPU basada en Arm, MCU basada en Arm y herramienta de búsqueda de terceros DSP

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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Paquete Pasadores Descargar
BGA (ZDU) 376 Ver opciones
NFBGA (ZWT) 361 Ver opciones
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Pedidos y calidad

Información incluida:
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  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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