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Microcontroladores (MCU) y procesadores
Procesadores digitales de señales (DSP)

TMS320VC5402

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Procesador de señal digital

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TMS320VC5402

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Detalles del producto

DSP type 1 C54x DSP (max) (MHz) 100 CPU 16-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) 0 to 0
DSP type 1 C54x DSP (max) (MHz) 100 CPU 16-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) 0 to 0
LQFP (PGE) 144 484 mm² 22 x 22
  • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
  • 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
  • 17-× 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
  • Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
  • Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Data Bus With a Bus-Holder Feature
  • Extended Addressing Mode for 1M × 16-Bit Maximum Addressable External Program Space
  • 4K x 16-Bit On-Chip ROM
  • 16K x 16-Bit Dual-Access On-Chip RAM
  • Single-Instruction-Repeat and Block-Repeat Operations for Program Code
  • Block-Memory-Move Instructions for Efficient Program and Data Management
  • Instructions With a 32-Bit Long Word Operand
  • Instructions With Two- or Three-Operand Reads
  • Arithmetic Instructions With Parallel Store and Parallel Load
  • Conditional Store Instructions
  • Fast Return From Interrupt
  • On-Chip Peripherals
    • Software-Programmable Wait-State Generator and Programmable Bank Switching
    • On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • Enhanced 8-Bit Parallel Host-Port Interface (HPI8)
    • Two 16-Bit Timers
    • Six-Channel Direct Memory Access (DMA) Controller
  • Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
  • CLKOUT Off Control to Disable CLKOUT
  • On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • 10-ns Single-Cycle Fixed-Point Instruction Execution Time (100 MIPS) for 3.3-V Power Supply (1.8-V Core)
  • Available in a 144-Pin Plastic Low-Profile Quad Flatpack (LQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix)


All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE:This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview (literature number SPRU307).
  • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
  • 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
  • 17-× 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
  • Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
  • Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Data Bus With a Bus-Holder Feature
  • Extended Addressing Mode for 1M × 16-Bit Maximum Addressable External Program Space
  • 4K x 16-Bit On-Chip ROM
  • 16K x 16-Bit Dual-Access On-Chip RAM
  • Single-Instruction-Repeat and Block-Repeat Operations for Program Code
  • Block-Memory-Move Instructions for Efficient Program and Data Management
  • Instructions With a 32-Bit Long Word Operand
  • Instructions With Two- or Three-Operand Reads
  • Arithmetic Instructions With Parallel Store and Parallel Load
  • Conditional Store Instructions
  • Fast Return From Interrupt
  • On-Chip Peripherals
    • Software-Programmable Wait-State Generator and Programmable Bank Switching
    • On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • Enhanced 8-Bit Parallel Host-Port Interface (HPI8)
    • Two 16-Bit Timers
    • Six-Channel Direct Memory Access (DMA) Controller
  • Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
  • CLKOUT Off Control to Disable CLKOUT
  • On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • 10-ns Single-Cycle Fixed-Point Instruction Execution Time (100 MIPS) for 3.3-V Power Supply (1.8-V Core)
  • Available in a 144-Pin Plastic Low-Profile Quad Flatpack (LQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix)


All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE:This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview (literature number SPRU307).

The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the '5402 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition, the '5402 includes the control mechanisms to manage interrupts, repeated operations, and function calls.

The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the '5402 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition, the '5402 includes the control mechanisms to manage interrupts, repeated operations, and function calls.
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Documentación técnica

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Tipo Título Fecha
* Data sheet TMS320VC5402 Fixed-Point Digital Signal Processor datasheet (Rev. G) 20 oct 2008
* Errata TMS320UC5402/TMS320VC5402 Digital Signal Processors Silicon Errata (Rev. D) 10 abr 2003
Application note TMS320VC5402 and TMS320UC5402 Bootloader (Rev. B) 03 nov 2004
User guide TMS320C54x Chip Support Library API Reference Guide (Rev. D) 05 may 2003
Application note Using the TMS320C5402 DSK Sine Program and evmdsk54x.dll 11 nov 2002
Application note Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402? DSP 24 oct 2002
Application note Bootloading the TMS320VC5402 in HPI Mode 29 abr 2002
User guide TMS320C54x DSP CPU and Peripherals Reference Set Volume 1 (Rev. G) 31 mar 2001
User guide TMS320C54x DSP Algebraic Instruction Set Reference Set Volume 3 (Rev. C) 31 ene 2001
User guide TMS320C54x DSP Mnemonic Instruction Set Reference Set Volume 2 (Rev. C) 31 ene 2001
Application note Interfacing the TLV320AIC10/11 Codec to the TMS320C5402 DSP 18 dic 2000
Application note Powering the TMS320VC5402 DSP Using the TPS60100, TPS76918, and the TPS3305-18 16 dic 1999
Application note TPS6010x/TPS6011x Charge Pump (Rev. A) 16 dic 1999
User guide TMS320C54x DSP Applications Guide Reference Set Volume 4 01 oct 1996

Diseño y desarrollo

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Placa de evaluación

TMDSDSK5416 — Kit básico TMS320C5416 DSP (DSK)

The TMS320C5416 DSP starter kit (DSK) is a low-cost development platform designed to speed the development of power-efficient applications based on TI's TMS320C54x DSPs. The kit, which provides new performance-enhancing features such as USB communications and true plug-and-play functionality, gives (...)
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Sonda de depuración

TMDSEMU560V2STM-U — Sonda de depuración USB de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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Sonda de depuración

TMDSEMU560V2STM-UE — Sonda de depuración USB y ethernet de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

No disponible en TI.com
Modelo de simulación

VC5402 GGU BSDL Model

SPRM063.ZIP (5 KB) - BSDL Model
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Modelo de simulación

VC5402 PGE BSDL Model

SPRM062.ZIP (5 KB) - BSDL Model
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Modelo de simulación

VC5402 PGE IBIS Model

SPRM252.ZIP (27 KB) - IBIS Model
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Herramienta de diseño

PROCESSORS-3P-SEARCH — MPU basada en Arm, MCU basada en Arm y herramienta de búsqueda de terceros DSP

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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LQFP (PGE) 144 Ver opciones
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