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TMS320VC5505

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低消費電力 C55x 固定小数点 DSP - 最大 100MHz、USB と LCD インターフェイスと FFT HWA と SAR ADC 搭載

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データシート
エラッタ

TMS320VC5505

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データシート ご注文はこちら

製品詳細

DSP type 1 C55x DSP (max) (MHz) 60, 100 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) to
DSP type 1 C55x DSP (max) (MHz) 60, 100 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) to
NFBGA (ZCH) 196 100 mm² 10 x 10
  • High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
    • 16.67-, 10-ns Instruction Cycle Time
    • 60-, 100-MHz Clock Rate
    • One/Two Instruction(s) Executed per Cycle
    • Dual Multipliers [Up to 200 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
    • Fully Software-Compatible With C55x Devices
    • Industrial Temperature Devices Available
  • 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
    • 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
  • 128K Bytes of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit)
    • 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
    • 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
    • 8-/16-Bit NOR Flash
    • Asynchronous Static RAM (SRAM)
  • Direct Memory Access (DMA) Controller
    • Four DMA With 4 Channels Each (16-Channels Total)
  • Three 32-Bit General-Purpose Timers
    • One Selectable as a Watchdog and/or GP
  • Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Serial-Port Interface (SPI) With Four Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Four Inter-IC Sound (I2S Bus™) for Data Transport
  • Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
    • USB 2.0 Full- and High-Speed Device
  • LCD Bridge With Asynchronous Interface
  • Tightly-Coupled FFT Hardware Accelerator
  • 10-Bit 4-Input Successive Approximation (SAR) ADC
  • Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain, Separate Power Supply
  • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
  • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
  • Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
  • On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, or I2C EEPROM
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 26 General-Purpose I/O (GPIO) Pins
  • (Multiplexed With Other Device Functions)
  • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
  • 1.05-V Core (60 MHz), 1.8-V, 2.5-V, 2.8-V, or 3.3-V I/Os
  • 1.3-V Core (100 MHz), 1.8-V, 2.5-V, 2.8-V, or 3.3-V I/Os
  • Applications:
    • Wireless Audio Devices (e.g., Headsets, Microphones, Speakerphones, etc.)
    • Echo Cancellation Headphones
    • Portable Medical Devices
    • Voice Applications
    • Industrial Controls
    • Fingerprint Biometrics
    • Software Defined Radio

All trademarks are the property of their respective owners.
  • High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
    • 16.67-, 10-ns Instruction Cycle Time
    • 60-, 100-MHz Clock Rate
    • One/Two Instruction(s) Executed per Cycle
    • Dual Multipliers [Up to 200 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
    • Fully Software-Compatible With C55x Devices
    • Industrial Temperature Devices Available
  • 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
    • 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
  • 128K Bytes of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit)
    • 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
    • 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
    • 8-/16-Bit NOR Flash
    • Asynchronous Static RAM (SRAM)
  • Direct Memory Access (DMA) Controller
    • Four DMA With 4 Channels Each (16-Channels Total)
  • Three 32-Bit General-Purpose Timers
    • One Selectable as a Watchdog and/or GP
  • Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Serial-Port Interface (SPI) With Four Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Four Inter-IC Sound (I2S Bus™) for Data Transport
  • Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
    • USB 2.0 Full- and High-Speed Device
  • LCD Bridge With Asynchronous Interface
  • Tightly-Coupled FFT Hardware Accelerator
  • 10-Bit 4-Input Successive Approximation (SAR) ADC
  • Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain, Separate Power Supply
  • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
  • Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
  • Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
  • On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, or I2C EEPROM
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 26 General-Purpose I/O (GPIO) Pins
  • (Multiplexed With Other Device Functions)
  • 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
  • 1.05-V Core (60 MHz), 1.8-V, 2.5-V, 2.8-V, or 3.3-V I/Os
  • 1.3-V Core (100 MHz), 1.8-V, 2.5-V, 2.8-V, or 3.3-V I/Os
  • Applications:
    • Wireless Audio Devices (e.g., Headsets, Microphones, Speakerphones, etc.)
    • Echo Cancellation Headphones
    • Portable Medical Devices
    • Voice Applications
    • Industrial Controls
    • Fingerprint Biometrics
    • Software Defined Radio

All trademarks are the property of their respective owners.

The TMS320VC5505 is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The TMS320VC5505 fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The TMS320VC5505 also includes four DMA controllers, each with 4 channels, providing data movements for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The VC5505 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM. Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). The DMA controller provides data movement for sixteen independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. This device also includesthree general-purpose timers with one configurable as a watchdog timer, and a analog phase-locked loop (APLL) clock generator.

In addition, the VC5505 includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.

The VC5505 is supported by the industry's award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments' algorithm standard, and the industry's largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The VC5505 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support

The TMS320VC5505 is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The TMS320VC5505 fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The TMS320VC5505 also includes four DMA controllers, each with 4 channels, providing data movements for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The VC5505 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM. Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). The DMA controller provides data movement for sixteen independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. This device also includesthree general-purpose timers with one configurable as a watchdog timer, and a analog phase-locked loop (APLL) clock generator.

In addition, the VC5505 includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.

The VC5505 is supported by the industry's award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments' algorithm standard, and the industry's largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The VC5505 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support
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種類 タイトル 最新の英語版をダウンロード 日付
* データシート TMS320VC5505 Fixed-Point Digital Signal Processor データシート (Rev. B) 2010年 2月 12日
* エラッタ TMS320VC5505/VC5504 Fixed-Point DSP Silicon Errata (Silicon Revision 1.4) (Rev. C) 2013年 1月 15日
ユーザー・ガイド TMS320C5515/14/05/04/VC05/VC04 DSP MMC/SD Card Controller User's Guide (Rev. B) 2015年 9月 30日
アプリケーション・ノート FFT Implementation on the TMS320VC5505, TMS320C5505, and TMS320C5515 DSPs (Rev. B) 2013年 1月 9日
ユーザー・ガイド Emulation and Trace Headers Technical Reference Manual (Rev. I) 2012年 8月 9日
ユーザー・ガイド TMS320C5515/05/VC05 DSP Successive Approx. Register (SAR) ADC User's Guide (Rev. C) 2012年 1月 13日
ユーザー・ガイド TMS320VC5505 DSP System User's Guide (Rev. C) 2012年 1月 12日
ユーザー・ガイド TMS320C55x DSP Peripherals Overview Reference Guide (Rev. K) 2011年 12月 15日
ユーザー・ガイド TMS320C55x Assembly Language Tools User's Guide (Rev. I) 2011年 11月 9日
ユーザー・ガイド TMS320C55x Optimizing C/C++ Compiler User's Guide (Rev. G) 2011年 11月 9日
アプリケーション・ノート Using the TMS320VC5505/04 Bootloader (Rev. A) 2010年 5月 10日
ユーザー・ガイド TMS320VC5505/04 DSP External Memory Interface (EMIF) User's Guide (Rev. A) 2010年 3月 17日
ユーザー・ガイド TMS320VC5505/5504 DSP Inter-IC Sound User's Guide (Rev. A) 2010年 1月 25日
ユーザー・ガイド TMS320C5515/05/VC05 DSP Liquid Crystal Display Controller User's Guide 2009年 9月 21日
ユーザー・ガイド TMS320C5515/14/05/04/VC05/VC04 DSP General-Purpose Input/Output User's Guide 2009年 9月 21日
ユーザー・ガイド TMS320C5515/14/05/04/VC05/VC04 DSP Inter-Integrated Circuit (I2C) Peripheral UG (Rev. A) 2009年 9月 21日
ユーザー・ガイド TMS320C5515/14/05/04/VC05/VC04 DSP Serial Peripheral Interface (SPI) UG 2009年 9月 21日
ユーザー・ガイド TMS320C5515/14/05/04/VC05/VC04 DSP Timer/Watchdog Timer User's Guide 2009年 9月 21日
ユーザー・ガイド TMS320C5515/14/05/04/VC05/VC04 DSP UART User's Guide 2009年 9月 21日
ユーザー・ガイド TMS320VC5505/5504 DSP Direct Memory Access (DMA) Controller User's Guide 2009年 9月 21日
ユーザー・ガイド TMS320VC5505/5504 DSP Real-Time Clock User's Guide 2009年 9月 21日
ユーザー・ガイド TMS320VC5505/5504 DSP Universal Serial Bus 2.0 (USB) User's Guide 2009年 9月 21日
製品概要 C5505 eZDSP UBS Stick Dev Tool Product Bulletin 2009年 9月 8日
その他の技術資料 C5504 and C5505 DSP Frequently Asked Questions (Rev. A) 2009年 8月 7日
製品概要 TMS320VC5504 and TMS320VC5505 DSPs Product Bulletin (Rev. C) 2009年 8月 6日
製品概要 Solutions for Personal Medical Application Development 2009年 6月 26日
ユーザー・ガイド TMS320C55x v3.x DSP Algebraic Instruction Set Reference Guide (Rev. E) 2009年 6月 24日
ユーザー・ガイド TMS320C55x v3.x DSP Mnemonic Instruction Set Reference Guide (Rev. E) 2009年 6月 24日
ユーザー・ガイド TMS320C55x DSP v3.x CPU Reference Guide (Rev. E) 2009年 6月 17日

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