TPS51100

활성

3A 소스/싱크 DDR 터미네이션 레귤레이터

제품 상세 정보

Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 0.75 Vout (max) (V) 1.25 Features S3/S5 Support Iq (typ) (mA) 0.5 Rating Catalog Operating temperature range (°C) -40 to 85 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, LPDDR3
Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 0.75 Vout (max) (V) 1.25 Features S3/S5 Support Iq (typ) (mA) 0.5 Rating Catalog Operating temperature range (°C) -40 to 85 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, LPDDR3
HVSSOP (DGQ) 10 14.7 mm² 3 x 4.9
  • Input Voltage Range: 4.75 V to 5.25 V
  • VLDOIN Voltage Range: 1.2 V to 3.6 V
  • 3-A Sink/Source Termination Regulator
    Includes Droop Compensation
  • Requires Only 20-μF Ceramic Output
    Capacitance
  • Supports Hi-Z in S3 and Soft-Off in S5
  • 1.2-V Input (VLDOIN) Helps Reduce Total
    Power Dissipation
  • Integrated Divider Tracks 0.5 VDDQSNS for
    VTT and VTTREF
  • Remote Sensing (VTTSNS)
  • ±20-mV Accuracy for VTT and VTTREF
  • 10-mA Buffered Reference (VTTREF)
  • Built-In Soft-Start, UVLO, and OCL
  • Thermal Shutdown
  • Supports JEDEC Specifications
  • Input Voltage Range: 4.75 V to 5.25 V
  • VLDOIN Voltage Range: 1.2 V to 3.6 V
  • 3-A Sink/Source Termination Regulator
    Includes Droop Compensation
  • Requires Only 20-μF Ceramic Output
    Capacitance
  • Supports Hi-Z in S3 and Soft-Off in S5
  • 1.2-V Input (VLDOIN) Helps Reduce Total
    Power Dissipation
  • Integrated Divider Tracks 0.5 VDDQSNS for
    VTT and VTTREF
  • Remote Sensing (VTTSNS)
  • ±20-mV Accuracy for VTT and VTTREF
  • 10-mA Buffered Reference (VTTREF)
  • Built-In Soft-Start, UVLO, and OCL
  • Thermal Shutdown
  • Supports JEDEC Specifications

The TPS51100 is a 3-A, sink/source tracking termination regulator. The device is specifically designed for low-cost and low-external component count systems where space is a premium.

The TPS51100 maintains fast transient response, only requiring 20 µF (2 × 10 µF) of ceramic output capacitance. The TPS51100 supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. The part also supports DDR3 VTT termination with VDDQ at 1.5 V (typical). In addition, the TPS51100 includes integrated sleep-state controls, placing VTT in Hi-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The TPS51100 is available in the thermally efficient 10-pin MSOP PowerPAD™ package and is specified from –40°C to 85°C.

The TPS51100 is a 3-A, sink/source tracking termination regulator. The device is specifically designed for low-cost and low-external component count systems where space is a premium.

The TPS51100 maintains fast transient response, only requiring 20 µF (2 × 10 µF) of ceramic output capacitance. The TPS51100 supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. The part also supports DDR3 VTT termination with VDDQ at 1.5 V (typical). In addition, the TPS51100 includes integrated sleep-state controls, placing VTT in Hi-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The TPS51100 is available in the thermally efficient 10-pin MSOP PowerPAD™ package and is specified from –40°C to 85°C.

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기술 문서

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모두 보기6
유형 직함 날짜
* Data sheet TPS51100 3-A Sink / Source DDR Termination Regulator datasheet (Rev. E) PDF | HTML 2014/12/17
Application note LDO Noise Demystified (Rev. B) PDF | HTML 2020/08/18
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 2020/07/09
Selection guide Power Management Guide 2018 (Rev. R) 2018/06/25
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017/08/09
User guide Using the TPS51100 2004/07/13

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

TPS51116EVM-001 — TPS51116 메모리 전원 솔루션, 동기 벅 컨트롤러 평가 모듈

The TPS51116EVM evaluation module (EVM) is a dual-output converter for DDR and DDRII memory modules. It uses a 10 A synchronous buck converter to provide the core voltage (VDDQ) for DDR memory modules. The EVM is designed to use a 4.5 V to 28 V supply voltage and a 4.75 V to (...)

사용 설명서: PDF
TI.com에서 구매할 수 없습니다
시뮬레이션 모델

TPS51100 PSpice Model

SLVC176.ZIP (473 KB) - PSpice Model
시뮬레이션 모델

TPS51100 TINA-TI Average Reference Design

SLVC203.ZIP (217 KB) - TINA-TI Reference Design
시뮬레이션 모델

TPS51100 TINA-TI Average Sink Reference Design (Rev. A)

SLVC177A.ZIP (217 KB) - TINA-TI Reference Design
시뮬레이션 모델

TPS51100 TINA-TI Average Spice Model

SLVC204.ZIP (7 KB) - TINA-TI Spice Model
시뮬레이션 모델

TPS51100 TINA-TI Transient Reference Design

SLVC206.ZIP (216 KB) - TINA-TI Reference Design
시뮬레이션 모델

TPS51100 TINA-TI Transient Spice Model

SLVC205.ZIP (7 KB) - TINA-TI Spice Model
패키지 다운로드
HVSSOP (DGQ) 10 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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