Product details

Technology family AS Bits (#) 9 Rating Catalog Operating temperature range (°C) 0 to 70
Technology family AS Bits (#) 9 Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (D) 14 51.9 mm² 8.65 x 6
  • Generate Either Odd or Even Parity forNine Data Lines
  • Cascadable for n-Bit Parity
  • Direct Bus Connection for Parity Generation or Checking by Using the Parity I/O Port
  • Glitch-Free Bus During Power Up/Down
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

  • Generate Either Odd or Even Parity forNine Data Lines
  • Cascadable for n-Bit Parity
  • Direct Bus Connection for Parity Generation or Checking by Using the Parity I/O Port
  • Glitch-Free Bus During Power Up/Down
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

The SN54AS286 and SN74AS286 universal 9-bit parity generators/checkers feature a local output for parity checking and a 48-mA bus-driving
parity input/output (I/O) port for parity generation/checking. The word-length capability is easily expanded by cascading.

The transmit () control input is implemented specifically to accommodate cascading. When is low, the parity tree is disabled and PARITY ERROR remains at a high logic level regardless of the input levels. When is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A-I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.

The I/O control circuitry was designed so that the I/O port remains in the high-impedance state during power up or power down to prevent bus glitches.

The SN54AS286 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS286 is characterized for operation from 0°C to 70°C.

 

 

 

The SN54AS286 and SN74AS286 universal 9-bit parity generators/checkers feature a local output for parity checking and a 48-mA bus-driving
parity input/output (I/O) port for parity generation/checking. The word-length capability is easily expanded by cascading.

The transmit () control input is implemented specifically to accommodate cascading. When is low, the parity tree is disabled and PARITY ERROR remains at a high logic level regardless of the input levels. When is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A-I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.

The I/O control circuitry was designed so that the I/O port remains in the high-impedance state during power up or power down to prevent bus glitches.

The SN54AS286 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS286 is characterized for operation from 0°C to 70°C.

 

 

 

Download

Similar products you might be interested in

open-in-new Compare alternates
Similar functionality to the compared device
SN74AHCT86 ACTIVE 4-ch, 2-input, 4.5-V to 5.5-V XOR (exclusive OR) gates with TTL-compatible CMOS inputs Larger voltage range (2V to 5.5V), longer average propagation delay (9ns)
SN74LVC1G386 ACTIVE Single 3-input, 1.65-V to 5.5-V XOR (exclusive OR) gate Voltage range (1.65V to 5.5V), average drive strength (24mA), average propagation delay (5.5ns)

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 1
Type Title Date
* Data sheet 9-Bit Parity Generators/Checker With Bus-Driver Parity I/O Port datasheet (Rev. B) 01 Dec 1994

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos